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systembus: all slaves should have an output buffer

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This commit is contained in:
Wesley W. Terpstra 2017-07-29 00:13:33 -07:00
parent eadf4e9fcc
commit 540256e24a
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/SystemBus.scala
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@ -38,7 +38,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
val toMemoryBus: TLOutwardNode = outwardNode val toMemoryBus: TLOutwardNode = outwardNode
val toSlave: TLOutwardNode = outwardNode val toSlave: TLOutwardNode = outwardBufNode
def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))