From 540256e24aad0a7d8d3f5e5f8b07090d1e10a155 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 29 Jul 2017 00:13:33 -0700 Subject: [PATCH] systembus: all slaves should have an output buffer --- src/main/scala/coreplex/SystemBus.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 595098f8..9fe8a56b 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -38,7 +38,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr val toMemoryBus: TLOutwardNode = outwardNode - val toSlave: TLOutwardNode = outwardNode + val toSlave: TLOutwardNode = outwardBufNode def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))