From 53d62cb69de2bd05a36f3594e4134fffab6994ef Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Sat, 15 Mar 2014 16:45:58 -0700 Subject: [PATCH] remove nondeterminism --- rocket/src/main/scala/ctrl.scala | 8 +++++++- rocket/src/main/scala/dpath_util.scala | 7 ++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index bdedf889..39ce01c5 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -412,7 +412,13 @@ class Control(implicit conf: RocketConfiguration) extends Module val id_csr_en = id_csr != CSR.N val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) - val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr) + + val legal_uint_csrs = new scala.collection.mutable.ArrayBuffer[Bits] + for (csr <- legal_csrs) { + legal_uint_csrs += UInt(csr) + } + + val id_csr_invalid = id_csr_en && !Vec(legal_uint_csrs).contains(id_csr_addr) val id_csr_privileged = id_csr_en && (id_csr_addr(11,10) === UInt(3) && id_csr_wen || id_csr_addr(11,10) === UInt(2) || diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index a0082388..34af1d8c 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -243,7 +243,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module for (i <- 0 until reg_uarch_counters.size) read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i) - io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) + val decoded_mapping = new scala.collection.mutable.ArrayBuffer[(Bool, Bits)] + for ((k, v) <- read_mapping) { + decoded_mapping += ((decoded_addr(k), v)) + } + + io.rw.rdata := Mux1H(decoded_mapping) io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) {