riscv/rocket-chip
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This reduces div/mul/D$ miss latency by 1 cycle.
This commit is contained in:
Andrew Waterman
2013-08-24 14:39:23 -07:00
parent d4a0db4575
commit 52e31f3298
3 changed files with 28 additions and 23 deletions
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rocket/src/main/scala/tlb.scala
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@ -120,7 +120,7 @@ class TLB(entries: Int) extends Module
val sx_array = Reg(Bits()) // supervisor execute permission
when (io.ptw.resp.valid) {
tag_ram(r_refill_waddr) := io.ptw.resp.bits.ppn
val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm(5,0)
val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm
ur_array := ur_array.bitSet(r_refill_waddr, perm(0))
uw_array := uw_array.bitSet(r_refill_waddr, perm(1))
ux_array := ux_array.bitSet(r_refill_waddr, perm(2))