riscv/rocket-chip
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add U bit to misa register

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Howard Mao 2016-07-22 14:22:51 -07:00
parent a43ad522dc
commit 51edd19e85
1 changed files with 1 additions and 0 deletions
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rocket/src/main/scala/csr.scala
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@ -238,6 +238,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val isa_string = "IM" + val isa_string = "IM" +
(if (usingVM) "S" else "") + (if (usingVM) "S" else "") +
(if (usingUser) "U" else "") +
(if (usingAtomics) "A" else "") + (if (usingAtomics) "A" else "") +
(if (usingFPU) "FD" else "") + (if (usingFPU) "FD" else "") +
(if (usingRoCC) "X" else "") (if (usingRoCC) "X" else "")