From 51edd19e85f9bfa6c2822c1253b51253e0df5154 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 22 Jul 2016 14:22:51 -0700 Subject: [PATCH] add U bit to misa register --- rocket/src/main/scala/csr.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 34f12f39..86090c2f 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -238,6 +238,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) val isa_string = "IM" + (if (usingVM) "S" else "") + + (if (usingUser) "U" else "") + (if (usingAtomics) "A" else "") + (if (usingFPU) "FD" else "") + (if (usingRoCC) "X" else "")