Add new junctions repo as submodule (contains externally facing buses and peripherals).

Bump all submodules.

src/main/scala/Configs.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import junctions._
 import uncore._
 import rocket._
 import rocket.Util._

src/main/scala/RocketChip.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import junctions._
 import uncore._
 import rocket._
 import rocket.Util._
@@ -192,7 +193,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
     } else {
       val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
       val conv1 = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams)
-      val conv2 = Module(new MemIONASTISlaveIOConverter)
+      val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
       val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
       arb.io.clients <> banks.map(_.outerTL)
       conv1.io.tl <> arb.io.managers.head
@@ -206,6 +207,6 @@ class OuterMemorySystem extends Module with TopLevelParameters {
 
   // Create a SerDes for backup memory port
   if(params(UseBackupMemoryPort)) {
-    VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels)
+    VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels, params(HTIFWidth))
   } else { io.mem <> mem_channels }
 }

src/main/scala/Testing.scala

@@ -66,7 +66,7 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets)
       } else { "\n" }
     }
 
-    val f = createOutputFile(s"${Driver.topComponent.name}.${Driver.chiselConfigClassName.get}.d")
+    val f = createOutputFile(s"${Driver.topComponent.get.name}.${Driver.chiselConfigClassName.get}.d")
     f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n"))
     f.close
   }

src/main/scala/Vlsi.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import junctions._
 import uncore._
 
 class MemDessert extends Module {
@@ -18,9 +19,10 @@ object VLSIUtils {
       mems: Seq[MemIO],
       backup: MemSerializedIO,
       en: Bool,
-      nMemChannels: Int) {
+      nMemChannels: Int,
+      htifWidth: Int) {
     val arb = Module(new MemIOArbiter(nMemChannels))
-    val mem_serdes = Module(new MemSerdes)
+    val mem_serdes = Module(new MemSerdes(htifWidth))
     mem_serdes.io.wide <> arb.io.outer
     mem_serdes.io.narrow <> backup
 

src/main/scala/ZscaleChip.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import junctions._
 import uncore._
 import rocket._
 import zscale._