From 51c42083d085fdd59f2be24dfc1dd61cbc756077 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 29 Jul 2015 17:56:19 -0700 Subject: [PATCH] Add new junctions repo as submodule (contains externally facing buses and peripherals). Bump all submodules. --- .gitmodules | 3 +++ Makefrag | 3 ++- chisel | 2 +- hardfloat | 2 +- junctions | 1 + project/build.scala | 5 +++-- rocket | 2 +- src/main/scala/Configs.scala | 1 + src/main/scala/RocketChip.scala | 5 +++-- src/main/scala/Testing.scala | 2 +- src/main/scala/Vlsi.scala | 6 ++++-- src/main/scala/ZscaleChip.scala | 1 + uncore | 2 +- zscale | 2 +- 14 files changed, 24 insertions(+), 13 deletions(-) create mode 160000 junctions diff --git a/.gitmodules b/.gitmodules index 8ccfce66..f1b451cd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -22,3 +22,6 @@ [submodule "zscale"] path = zscale url = https://github.com/ucb-bar/zscale +[submodule "junctions"] + path = junctions + url = https://github.com/ucb-bar/junctions diff --git a/Makefrag b/Makefrag index 3ecde4c2..1fec0ce4 100644 --- a/Makefrag +++ b/Makefrag @@ -14,7 +14,8 @@ SHELL := /bin/bash CHISEL_ARGS := $(MODEL) --W0W --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) src_path = src/main/scala -chisel_srcs = $(base_dir)/$(src_path)/*.scala $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/zscale/$(src_path)/*.scala $(SRC_EXTENSION) +default_submodules = . junctions uncore hardfloat rocket zscale +chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules))) disasm := 2> which_disasm := $(shell which spike-dasm) diff --git a/chisel b/chisel index cc51775d..8ae53131 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit cc51775dda66db587b01fee4d29d22c49121fdb5 +Subproject commit 8ae531312ff1e1670d690b61297f275474f92bd6 diff --git a/hardfloat b/hardfloat index e2e06ff6..2f5eebd7 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit e2e06ff615d031be6c7d696b52718ca16cd9c87b +Subproject commit 2f5eebd75ff6bdbf10068bbad9fe948bf979d081 diff --git a/junctions b/junctions new file mode 160000 index 00000000..6152b186 --- /dev/null +++ b/junctions @@ -0,0 +1 @@ +Subproject commit 6152b1863ef11df83cf7aa5ecc4e4fd0f046e95f diff --git a/project/build.scala b/project/build.scala index a248ce9a..cd5ae60a 100644 --- a/project/build.scala +++ b/project/build.scala @@ -17,8 +17,9 @@ object BuildSettings extends Build { lazy val chisel = project lazy val hardfloat = project.dependsOn(chisel) - lazy val uncore = project.dependsOn(hardfloat) - lazy val rocket = project.dependsOn(uncore) + lazy val junctions = project.dependsOn(chisel) + lazy val uncore = project.dependsOn(junctions) + lazy val rocket = project.dependsOn(hardfloat,uncore) lazy val zscale = project.dependsOn(rocket) lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale) diff --git a/rocket b/rocket index d819fb28..0eefb35b 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit d819fb28c3370747475d7c5f4b641723cab1fd0c +Subproject commit 0eefb35b2e8d5f8dd975c460f446ad4f232d8ef0 diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 70734ee3..8dc7a5ca 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -3,6 +3,7 @@ package rocketchip import Chisel._ +import junctions._ import uncore._ import rocket._ import rocket.Util._ diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 3708817d..c261f2c0 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -3,6 +3,7 @@ package rocketchip import Chisel._ +import junctions._ import uncore._ import rocket._ import rocket.Util._ @@ -192,7 +193,7 @@ class OuterMemorySystem extends Module with TopLevelParameters { } else { val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams) val conv1 = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams) - val conv2 = Module(new MemIONASTISlaveIOConverter) + val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits))) val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs)) arb.io.clients <> banks.map(_.outerTL) conv1.io.tl <> arb.io.managers.head @@ -206,6 +207,6 @@ class OuterMemorySystem extends Module with TopLevelParameters { // Create a SerDes for backup memory port if(params(UseBackupMemoryPort)) { - VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels) + VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels, params(HTIFWidth)) } else { io.mem <> mem_channels } } diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index 9f05cdcf..ad197d6c 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -66,7 +66,7 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets) } else { "\n" } } - val f = createOutputFile(s"${Driver.topComponent.name}.${Driver.chiselConfigClassName.get}.d") + val f = createOutputFile(s"${Driver.topComponent.get.name}.${Driver.chiselConfigClassName.get}.d") f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n")) f.close } diff --git a/src/main/scala/Vlsi.scala b/src/main/scala/Vlsi.scala index 2ce0802e..22007e9d 100644 --- a/src/main/scala/Vlsi.scala +++ b/src/main/scala/Vlsi.scala @@ -3,6 +3,7 @@ package rocketchip import Chisel._ +import junctions._ import uncore._ class MemDessert extends Module { @@ -18,9 +19,10 @@ object VLSIUtils { mems: Seq[MemIO], backup: MemSerializedIO, en: Bool, - nMemChannels: Int) { + nMemChannels: Int, + htifWidth: Int) { val arb = Module(new MemIOArbiter(nMemChannels)) - val mem_serdes = Module(new MemSerdes) + val mem_serdes = Module(new MemSerdes(htifWidth)) mem_serdes.io.wide <> arb.io.outer mem_serdes.io.narrow <> backup diff --git a/src/main/scala/ZscaleChip.scala b/src/main/scala/ZscaleChip.scala index 38108e82..bcb6f5a1 100644 --- a/src/main/scala/ZscaleChip.scala +++ b/src/main/scala/ZscaleChip.scala @@ -3,6 +3,7 @@ package rocketchip import Chisel._ +import junctions._ import uncore._ import rocket._ import zscale._ diff --git a/uncore b/uncore index 9da93383..1ea793c0 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 9da933836eaeaf8825feefa20cecda1a58af35d0 +Subproject commit 1ea793c0404dc71600e86fca34ac3d1e60e26a14 diff --git a/zscale b/zscale index 1d2c1ef4..bde94d4e 160000 --- a/zscale +++ b/zscale @@ -1 +1 @@ -Subproject commit 1d2c1ef49b00f04ca9c60599fbd2af6d4fe6aa60 +Subproject commit bde94d4e739b67661f30750a7a4b7fbbf4b1d2f2