riscv/rocket-chip
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Merge pull request #1097 from freechipsproject/itim-error

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More ITIM error-handling improvements
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Wesley W. Terpstra 2017-11-09 00:17:48 -08:00 committed by GitHub
commit 50ce3f5086
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1 changed files with 4 additions and 4 deletions
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src/main/scala/rocket/ICache.scala
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@ -255,7 +255,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val s1_clk_en = s1_valid || s1_slaveValid val s1_clk_en = s1_valid || s1_slaveValid
val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en) val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en)
val s2_hit_way = OHToUInt(s2_tag_hit) val s2_hit_way = OHToUInt(s2_tag_hit)
val s2_scratchpad_word_addr = Cat(s2_hit_way, io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8))) val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8)))
val s2_dout = RegEnable(s1_dout, s1_clk_en) val s2_dout = RegEnable(s1_dout, s1_clk_en)
val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)
@ -302,7 +302,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr) assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid) when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) { && s2_valid && s2_data_decoded.error && !s2_tag_disparity) {
// handle correctable errors on CPU accesses to the scratchpad. // handle correctable errors on CPU accesses to the scratchpad.
// if there is an in-flight slave-port access to the scratchpad, // if there is an in-flight slave-port access to the scratchpad,
// report the a miss but don't correct the error (as there is // report the a miss but don't correct the error (as there is
@ -313,9 +313,9 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
respValid := s2_slaveValid || (respValid && !tl.d.ready) respValid := s2_slaveValid || (respValid && !tl.d.ready)
val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid) val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid)
when (s2_slaveValid) { when (s2_slaveValid) {
when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true }
def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i))
s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt
} }