From 9b16d25861668509144ef1fc91c504b38f7c47a0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Nov 2017 16:46:25 -0800 Subject: [PATCH 1/3] Fix reporting of ITIM error addresses on slave-port accesses --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 872ebc01..cc998775 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -255,7 +255,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s1_clk_en = s1_valid || s1_slaveValid val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en) val s2_hit_way = OHToUInt(s2_tag_hit) - val s2_scratchpad_word_addr = Cat(s2_hit_way, io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8))) + val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8))) val s2_dout = RegEnable(s1_dout, s1_clk_en) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout) From 5c1b34d854526581a9eb68a76f434b7e6e0dd7fb Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Nov 2017 16:46:57 -0800 Subject: [PATCH 2/3] Don't report a TL error if overwriting a whole ITIM word --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index cc998775..82ca13d4 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -313,7 +313,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } respValid := s2_slaveValid || (respValid && !tl.d.ready) - val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable, s2_slaveValid) + val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid) when (s2_slaveValid) { when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) From bb9d8264e279eae3c2220ce47b6a7730c11c940a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Nov 2017 16:47:25 -0800 Subject: [PATCH 3/3] "Correct" ITIM uncorrectable errors This permits forward progress when a core wants to handle its own uncorrectable ITIM errors. Previously, another core had to do it. --- src/main/scala/rocket/ICache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 82ca13d4..dce99de3 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -302,7 +302,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr) when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid) - && s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) { + && s2_valid && s2_data_decoded.error && !s2_tag_disparity) { // handle correctable errors on CPU accesses to the scratchpad. // if there is an in-flight slave-port access to the scratchpad, // report the a miss but don't correct the error (as there is @@ -315,7 +315,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) respValid := s2_slaveValid || (respValid && !tl.d.ready) val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !(edge_in.get.hasData(s1_a) && s1_a.mask.andR), s2_slaveValid) when (s2_slaveValid) { - when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } + when (edge_in.get.hasData(s1_a) || s2_data_decoded.error) { s3_slaveValid := true } def byteEn(i: Int) = !(edge_in.get.hasData(s1_a) && s1_a.mask(i)) s1s3_slaveData := (0 until wordBits/8).map(i => Mux(byteEn(i), s2_data_decoded.corrected, s1s3_slaveData)(8*(i+1)-1, 8*i)).asUInt }