riscv/rocket-chip
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bump chisel

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Donggyu Kim authored and Yunsup Lee committed 2014-09-25 06:46:58 -07:00
1 parent 60d90f5230
commit 4fe48f5a0a
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chisel
+1 -1
Submodule chisel updated: d7e913088f...e78ebbb858.
src/main/scala/Backends.scala
+1 -1
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@@ -62,7 +62,7 @@ class RocketChipBackend extends VerilogBackend
initMap += (c -> init) initMap += (c -> init)
} }
transforms += {c => collectNodesIntoComp} transforms += collectNodesIntoComp
transforms += addTopLevelPin transforms += addTopLevelPin
transforms += addMemPin transforms += addMemPin
} }