From 4fe48f5a0a53e4ef6e7677a7cd3dd6c6fd2df58b Mon Sep 17 00:00:00 2001
From: Donggyu Kim <dgkim@eecs.berkeley.edu>
Date: Tue, 23 Sep 2014 16:56:32 -0700
Subject: [PATCH] bump chisel

---
 chisel                        | 2 +-
 src/main/scala/Backends.scala | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/chisel b/chisel
index d7e91308..e78ebbb8 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit d7e913088f840cff42d56920ab323c9b5f399b6f
+Subproject commit e78ebbb858f3d7f426128aa85380723c2ab61064
diff --git a/src/main/scala/Backends.scala b/src/main/scala/Backends.scala
index c6bd0d92..de587c33 100644
--- a/src/main/scala/Backends.scala
+++ b/src/main/scala/Backends.scala
@@ -62,7 +62,7 @@ class RocketChipBackend extends VerilogBackend
     initMap += (c -> init)
   }
 
-  transforms += {c => collectNodesIntoComp}
+  transforms += collectNodesIntoComp
   transforms += addTopLevelPin
   transforms += addMemPin
 }