bump chisel

2014-09-23 16:56:32 -07:00
parent 60d90f5230
commit 4fe48f5a0a
2 changed files with 2 additions and 2 deletions
--- a/src/main/scala/Backends.scala
+++ b/src/main/scala/Backends.scala
@ -62,7 +62,7 @@ class RocketChipBackend extends VerilogBackend
    initMap += (c -> init)
  }

-  transforms += {c => collectNodesIntoComp}
+  transforms += collectNodesIntoComp
  transforms += addTopLevelPin
  transforms += addMemPin
 }