From 4eface8a9e9a3599c4fcb2f096ed581cc5a7d253 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 12 Jul 2017 16:20:22 -0700 Subject: [PATCH] rocket: do not require FIFO order for memory-like regions --- src/main/scala/coreplex/RocketTiles.scala | 6 +++--- src/main/scala/rocket/HellaCache.scala | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index fbacc17b..ffe79ef2 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -61,7 +61,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { case SynchronousCrossing(params) => { val wrapper = LazyModule(new SyncRocketTile(c, i)(pWithExtra)) val buffer = LazyModule(new TLBuffer(params)) - val fixer = LazyModule(new TLFIFOFixer) + val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) buffer.node :=* wrapper.masterNode fixer.node :=* buffer.node tile_splitter.node :=* fixer.node @@ -79,7 +79,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra)) val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) val source = LazyModule(new TLAsyncCrossingSource(sync)) - val fixer = LazyModule(new TLFIFOFixer) + val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) sink.node :=* wrapper.masterNode fixer.node :=* sink.node tile_splitter.node :=* fixer.node @@ -99,7 +99,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform { val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra)) val sink = LazyModule(new TLRationalCrossingSink(direction)) val source = LazyModule(new TLRationalCrossingSource) - val fixer = LazyModule(new TLFIFOFixer) + val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) sink.node :=* wrapper.masterNode fixer.node :=* sink.node tile_splitter.node :=* fixer.node diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 8adc2dd8..e7d506a8 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -183,8 +183,10 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) val io = new HellaCacheBundle(outer) val tl_out = io.mem(0) - // IOMSHRs must be FIFO - edge.manager.requireFifo() + // IOMSHRs must be FIFO for all regions with effects + edge.manager.managers.foreach { m => + require (m.fifoId == Some(0) || !TLFIFOFixer.allUncacheable(m)) + } } object HellaCache {