riscv/rocket-chip
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cleanup

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This commit is contained in:
Rimas Avizienis 2011-11-04 20:52:21 -07:00
parent 2db9ee12bc
commit 4d64099103
4 changed files with 22 additions and 18 deletions
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11
rocket/src/main/scala/ctrl.scala
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@ -322,14 +322,12 @@ class rocketCtrl extends Component
} }
// replay execute stage PC when the D$ is blocked // replay execute stage PC when the D$ is blocked
// val replay_mem_pc = mem_reg_mem_val && (mem_reg_mem_cmd != M_FLA) && !io.dmem.req_rdy;
val replay_ex = ex_reg_mem_val && !io.dmem.req_rdy; val replay_ex = ex_reg_mem_val && !io.dmem.req_rdy;
// replay memory stage PC+4 on a D$ load miss
// replay execute stage PC on a D$ load miss
val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD); val mem_cmd_load = mem_reg_mem_val && (mem_reg_mem_cmd === M_XRD);
// val replay_mem_pc_plus4 = mem_cmd_load && !io.dmem.resp_val;
val replay_mem = io.dmem.resp_miss; val replay_mem = io.dmem.resp_miss;
// val kill_ex = replay_mem_pc | replay_mem_pc_plus4 | mem_reg_privileged;
val kill_ex = replay_ex | replay_mem | mem_reg_privileged; val kill_ex = replay_ex | replay_mem | mem_reg_privileged;
val kill_mem = io.dpath.exception; val kill_mem = io.dpath.exception;
@ -339,14 +337,13 @@ class rocketCtrl extends Component
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(io.dpath.exception || mem_reg_eret, PC_PCR, Mux(io.dpath.exception || mem_reg_eret, PC_PCR,
Mux(replay_mem || mem_reg_privileged, PC_MEM4, Mux(replay_ex || replay_mem || mem_reg_privileged, PC_EX,
Mux(replay_ex, PC_EX,
Mux(!ex_reg_btb_hit && br_taken, PC_BR, Mux(!ex_reg_btb_hit && br_taken, PC_BR,
Mux(ex_reg_btb_hit && !br_taken, PC_EX4, Mux(ex_reg_btb_hit && !br_taken, PC_EX4,
Mux(jr_taken, PC_JR, Mux(jr_taken, PC_JR,
Mux(j_taken, PC_J, Mux(j_taken, PC_J,
Mux(io.dpath.btb_hit, PC_BTB, Mux(io.dpath.btb_hit, PC_BTB,
PC_4)))))))); PC_4)))))));
io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken & ~kill_ex & ~kill_mem; io.dpath.wen_btb := ~ex_reg_btb_hit & br_taken & ~kill_ex & ~kill_mem;

3
rocket/src/main/scala/dcache.scala
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@ -110,7 +110,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
val r_cpu_req_addr = Reg(resetVal = Bits(0, addrbits)); val r_cpu_req_addr = Reg(resetVal = Bits(0, addrbits));
val r_cpu_req_val = Reg(resetVal = Bool(false)); val r_cpu_req_val = Reg(resetVal = Bool(false));
// val r_cpu_req_data = Reg(resetVal = Bits(0,64));
val r_cpu_req_cmd = Reg(resetVal = Bits(0,4)); val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
val r_cpu_req_type = Reg(resetVal = Bits(0,3)); val r_cpu_req_type = Reg(resetVal = Bits(0,3));
val r_cpu_req_tag = Reg(resetVal = Bits(0,5)); val r_cpu_req_tag = Reg(resetVal = Bits(0,5));
@ -119,7 +118,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
val p_store_addr = Reg(resetVal = Bits(0,64)); val p_store_addr = Reg(resetVal = Bits(0,64));
val p_store_cmd = Reg(resetVal = Bits(0,4)); val p_store_cmd = Reg(resetVal = Bits(0,4));
val p_store_type = Reg(resetVal = Bits(0,3)); val p_store_type = Reg(resetVal = Bits(0,3));
// val p_store_wmask = Reg(resetVal = Bits(0,64));
val p_store_valid = Reg(resetVal = Bool(false)); val p_store_valid = Reg(resetVal = Bool(false));
val req_load = (r_cpu_req_cmd === M_XRD); val req_load = (r_cpu_req_cmd === M_XRD);
@ -222,7 +220,6 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
val addr_match = (r_cpu_req_addr(tagmsb, offsetlsb) === p_store_addr(tagmsb, offsetlsb)); val addr_match = (r_cpu_req_addr(tagmsb, offsetlsb) === p_store_addr(tagmsb, offsetlsb));
val ldst_conflict = r_cpu_req_val && req_load && p_store_valid && addr_match; val ldst_conflict = r_cpu_req_val && req_load && p_store_valid && addr_match;
// val drain_store = ((state === s_ready) && p_store_valid && (!r_cpu_req_val || !tag_match || !req_load || addr_match))
val drain_store = val drain_store =
(state === s_ready) && p_store_valid && (state === s_ready) && p_store_valid &&
(!(io.cpu.req_val && (io.cpu.req_cmd === M_XRD)) || (!(io.cpu.req_val && (io.cpu.req_cmd === M_XRD)) ||

3
rocket/src/main/scala/dpath.scala
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@ -137,8 +137,7 @@ class rocketDpath extends Component
Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix, Mux(io.ctrl.sel_pc === PC_JR, ex_jr_target.toUFix,
Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_pcr(31,0).toUFix, Mux(io.ctrl.sel_pc === PC_PCR, mem_reg_pcr(31,0).toUFix,
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc, Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
Mux(io.ctrl.sel_pc === PC_MEM4, mem_reg_pc_plus4, UFix(0, 32))))))))));
UFix(0, 32)))))))))));
when (!io.host.start){ when (!io.host.start){
if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC; if_reg_pc <== UFix(0, 32); //32'hFFFF_FFFC;

23
rocket/src/main/scala/icache.scala
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@ -24,7 +24,8 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
val resp_val = Bool('output); val resp_val = Bool('output);
} }
class ioICacheDM extends Bundle() { class ioICacheDM extends Bundle()
{
val cpu = new ioImem(); val cpu = new ioImem();
val mem = new ioIcache().flip(); val mem = new ioIcache().flip();
} }
@ -51,14 +52,22 @@ class rocketICacheDM(lines: Int, addrbits : Int) extends Component {
val state = Reg(resetVal = s_reset); val state = Reg(resetVal = s_reset);
val r_cpu_req_addr = Reg(Bits(0, addrbits)); val r_cpu_req_addr = Reg(Bits(0, addrbits));
when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) { r_cpu_req_addr <== io.cpu.req_addr; } when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
r_cpu_req_addr <== io.cpu.req_addr;
}
val r_cpu_req_val = Reg(Bool(false)); val r_cpu_req_val = Reg(Bool(false));
when ((state === s_ready) || (state === s_resolve_miss)) { r_cpu_req_val <== io.cpu.req_val; } when ((state === s_ready) || (state === s_resolve_miss)) {
otherwise { r_cpu_req_val <== Bool(false); } r_cpu_req_val <== io.cpu.req_val;
}
otherwise {
r_cpu_req_val <== Bool(false);
}
val refill_count = Reg(resetVal = UFix(0,2)); val refill_count = Reg(resetVal = UFix(0,2));
when (io.mem.resp_val) { refill_count <== refill_count + UFix(1); } when (io.mem.resp_val) {
refill_count <== refill_count + UFix(1);
}
// tag array // tag array
val tag_wdata = r_cpu_req_addr(tagmsb, taglsb); val tag_wdata = r_cpu_req_addr(tagmsb, taglsb);
@ -72,7 +81,9 @@ class rocketICacheDM(lines: Int, addrbits : Int) extends Component {
val vb_array = Reg(resetVal = Bits(0, lines)); val vb_array = Reg(resetVal = Bits(0, lines));
val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb))); val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
when ((state === s_refill_wait) && io.mem.resp_val) { vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1)); } when ((state === s_refill_wait) && io.mem.resp_val) {
vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
}
val tag_match = vb_rdata.toBool && (tag_lookup === r_cpu_req_addr(tagmsb, taglsb)); val tag_match = vb_rdata.toBool && (tag_lookup === r_cpu_req_addr(tagmsb, taglsb));