diff --git a/rocket b/rocket
index d91be2b5..c521632f 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit d91be2b545ea0eb704bf3c2b02b5d200f27426fa
+Subproject commit c521632f6415cc703fdd8212f157f8ac9810d352
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 06ed83f1..e51440d1 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -195,7 +195,8 @@ class BaseConfig extends Config (
       case UsePerfCounters => true
       case FastLoadWord => true
       case FastLoadByte => false
-      case FastMulDiv => true
+      case MulDivUnroll => 8
+      case DivEarlyOut => true
       case XLen => 64
       case UseFPU => {
         val env = if(site(UseVM)) List("p","v") else List("p")
@@ -444,7 +445,8 @@ class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
 class WithSmallCores extends Config (
     topDefinitions = { (pname,site,here) => pname match {
       case UseFPU => false
-      case FastMulDiv => false
+      case MulDivUnroll => 1
+      case DivEarlyOut => false  
       case NTLBEntries => 4
       case BtbKey => BtbParameters(nEntries = 0)
       case StoreDataQueueDepth => 2