riscv/rocket-chip
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make the connection of FPU ports optional per accelerator

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This commit is contained in:
Howard Mao 2015-12-01 16:48:05 -08:00
parent 0b15b19381
commit 4833d41dbc
1 changed files with 16 additions and 8 deletions
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24
rocket/src/main/scala/tile.scala
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@ -11,6 +11,7 @@ case object CoreName extends Field[String]
case object BuildRoCC extends Field[Seq[Parameters => RoCC]] case object BuildRoCC extends Field[Seq[Parameters => RoCC]]
case object RoccOpcodes extends Field[Seq[OpcodeSet]] case object RoccOpcodes extends Field[Seq[OpcodeSet]]
case object RoccAcceleratorMemChannels extends Field[Seq[Int]] case object RoccAcceleratorMemChannels extends Field[Seq[Int]]
case object RoccUseFPU extends Field[Seq[Boolean]]
abstract class Tile(resetSignal: Bool = null) abstract class Tile(resetSignal: Bool = null)
(implicit p: Parameters) extends Module(_reset = resetSignal) { (implicit p: Parameters) extends Module(_reset = resetSignal) {
@ -19,6 +20,8 @@ abstract class Tile(resetSignal: Bool = null)
val roccMemChannels = p(RoccAcceleratorMemChannels) val roccMemChannels = p(RoccAcceleratorMemChannels)
val usingRocc = !buildRocc.isEmpty val usingRocc = !buildRocc.isEmpty
val nRocc = buildRocc.size val nRocc = buildRocc.size
val roccUseFPU = p(RoccUseFPU)
val nFPUPorts = roccUseFPU.filter(useFPU => useFPU).size
val nDCachePorts = 2 + nRocc val nDCachePorts = 2 + nRocc
val nPTWPorts = 2 + 3 * nRocc val nPTWPorts = 2 + 3 * nRocc
val nCachedTileLinkPorts = 1 val nCachedTileLinkPorts = 1
@ -86,15 +89,20 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
rocc rocc
} }
fpuOpt.foreach { fpu => if (nFPUPorts > 0) {
val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nRocc)) fpuOpt.foreach { fpu =>
fpArb.io.in_req <> roccs.map(_.io.fpu_req) val fpArb = Module(new InOrderArbiter(new FPInput, new FPResult, nFPUPorts))
roccs.zip(fpArb.io.in_resp).foreach { val fp_roccs = roccs.zip(roccUseFPU)
case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp .filter { case (_, useFPU) => useFPU }
.map { case (rocc, _) => rocc }
fpArb.io.in_req <> fp_roccs.map(_.io.fpu_req)
fp_roccs.zip(fpArb.io.in_resp).foreach {
case (rocc, fpu_resp) => rocc.io.fpu_resp <> fpu_resp
}
fpu.io.cp_req <> fpArb.io.out_req
fpArb.io.out_resp <> fpu.io.cp_resp
} }
fpu.io.cp_req <> fpArb.io.out_req }
fpArb.io.out_resp <> fpu.io.cp_resp
}
core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _) core.io.rocc.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)
core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _) core.io.rocc.interrupt := roccs.map(_.io.interrupt).reduce(_ || _)