From 47a2097507154c67512b625747715456edb532cc Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 6 Mar 2012 17:33:11 -0800 Subject: [PATCH] unified coherence trait functions --- rocket/src/main/scala/coherence.scala | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala index a04b7096..bda67671 100644 --- a/rocket/src/main/scala/coherence.scala +++ b/rocket/src/main/scala/coherence.scala @@ -126,7 +126,15 @@ trait ThreeStateIncoherence extends CoherencePolicy { val (read, write) = cpuCmdToRW(cmd) Mux(write, tileDirty, state) } - + def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = X_INIT_READ_EXCLUSIVE + def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = { + val (read, write) = cpuCmdToRW(cmd) + Mux(write, tileDirty, tileClean) + } + def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false) + def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = state + def probeReplyHasData (reply: ProbeReply): Bool = Bool(false) + def transactionInitHasData (init: TransactionInit): Bool = (init.t_type != X_INIT_WRITE_UNCACHED) } trait FourStateCoherence extends CoherencePolicy { @@ -162,7 +170,7 @@ trait FourStateCoherence extends CoherencePolicy { val (read, write) = cpuCmdToRW(cmd) Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED) } - def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = { + def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = { MuxLookup(incoming.t_type, tileInvalid, Array( X_REP_READ_SHARED -> tileShared, X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),