riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Disable printf/assert during reset

Browse Source
This commit is contained in:
Andrew Waterman 2016-04-01 16:40:13 -07:00 committed by Henry Cook
parent cd9e07d8e7
commit 46d7dceb1e
3 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vsim/Makefrag
View File

@ -46,7 +46,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(sim_dir)/libdramsim.a \ $(sim_dir)/libdramsim.a \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).verbose \ +define+PRINTF_COND=$(TB).printf_cond \
+libext+.v \ +libext+.v \
#-------------------------------------------------------------------- #--------------------------------------------------------------------

1
vsrc/ZscaleTestHarness.v
View File

@ -33,6 +33,7 @@ module ZscaleTestHarness;
reg [ 63:0] max_cycles = 0; reg [ 63:0] max_cycles = 0;
reg [ 63:0] trace_count = 0; reg [ 63:0] trace_count = 0;
reg verbose = 0; reg verbose = 0;
wire printf_cond = verbose && !reset;
integer stderr = 32'h80000002; integer stderr = 32'h80000002;
integer i; integer i;
reg [127:0] image [8191:0]; reg [127:0] image [8191:0];

1
vsrc/rocketTestHarness.v
View File

@ -78,6 +78,7 @@ module rocketTestHarness;
reg stats_active = 0; reg stats_active = 0;
reg stats_tracking = 0; reg stats_tracking = 0;
reg verbose = 0; reg verbose = 0;
wire printf_cond = verbose && !reset;
integer stderr = 32'h80000002; integer stderr = 32'h80000002;
`include `TBVFRAG `include `TBVFRAG