diff --git a/vsim/Makefrag b/vsim/Makefrag
index a6e9e143..54cd16df 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -46,7 +46,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(sim_dir)/libdramsim.a \
 	+incdir+$(generated_dir) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND=$(TB).verbose \
+	+define+PRINTF_COND=$(TB).printf_cond \
 	+libext+.v \
 
 #--------------------------------------------------------------------
diff --git a/vsrc/ZscaleTestHarness.v b/vsrc/ZscaleTestHarness.v
index 7e8bbc35..a7972304 100644
--- a/vsrc/ZscaleTestHarness.v
+++ b/vsrc/ZscaleTestHarness.v
@@ -33,6 +33,7 @@ module ZscaleTestHarness;
   reg [  63:0] max_cycles = 0;
   reg [  63:0] trace_count = 0;
   reg          verbose = 0;
+  wire         printf_cond = verbose && !reset;
   integer      stderr = 32'h80000002;
   integer      i;
   reg [127:0]  image [8191:0];
diff --git a/vsrc/rocketTestHarness.v b/vsrc/rocketTestHarness.v
index a1727eda..8ee33dc6 100644
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@@ -78,6 +78,7 @@ module rocketTestHarness;
   reg          stats_active = 0;
   reg          stats_tracking = 0;
   reg          verbose = 0;
+  wire         printf_cond = verbose && !reset;
   integer      stderr = 32'h80000002;
 
 `include `TBVFRAG