riscv/rocket-chip
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fix scr parameterization bug

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This commit is contained in:
Yunsup Lee 2013-08-24 22:42:51 -07:00
parent 2ca5127785
commit 44e92edf92
2 changed files with 7 additions and 3 deletions
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3
rocket/src/main/scala/dpath_util.scala
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@ -114,6 +114,9 @@ class PCR(implicit conf: RocketConfiguration) extends Component
val wdata = Bits(INPUT, conf.xprlen) val wdata = Bits(INPUT, conf.xprlen)
} }
// there is a fixed constant related to this in PCRReq.addr
require(log2Up(conf.nxpr) == 5)
val status = new Status().asOutput val status = new Status().asOutput
val ptbr = UFix(OUTPUT, PADDR_BITS) val ptbr = UFix(OUTPUT, PADDR_BITS)
val evec = UFix(OUTPUT, VADDR_BITS) val evec = UFix(OUTPUT, VADDR_BITS)

7
rocket/src/main/scala/htif.scala
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@ -21,7 +21,7 @@ class HostIO(val w: Int) extends Bundle
class PCRReq extends Bundle class PCRReq extends Bundle
{ {
val rw = Bool() val rw = Bool()
val addr = Bits(width = 6) val addr = Bits(width = 5)
val data = Bits(width = 64) val data = Bits(width = 64)
} }
@ -237,6 +237,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
} }
} }
val scr_addr = addr(log2Up(nSCR)-1, 0)
val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)} val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)}
for (i <- 0 until scr_rdata.size) for (i <- 0 until scr_rdata.size)
scr_rdata(i) := io.scr.rdata(i) scr_rdata(i) := io.scr.rdata(i)
@ -245,10 +246,10 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
io.scr.wen := false io.scr.wen := false
io.scr.wdata := pcr_wdata io.scr.wdata := pcr_wdata
io.scr.waddr := pcr_addr.toUFix io.scr.waddr := scr_addr.toUFix
when (state === state_pcr_req && pcr_coreid === Fix(-1)) { when (state === state_pcr_req && pcr_coreid === Fix(-1)) {
io.scr.wen := cmd === cmd_writecr io.scr.wen := cmd === cmd_writecr
pcrReadData := scr_rdata(pcr_addr) pcrReadData := scr_rdata(scr_addr)
state := state_tx state := state_tx
} }