diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 65f377b2..9a861bca 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -113,6 +113,9 @@ class PCR(implicit conf: RocketConfiguration) extends Component
       val rdata = Bits(OUTPUT, conf.xprlen)
       val wdata = Bits(INPUT, conf.xprlen)
     }
+
+    // there is a fixed constant related to this in PCRReq.addr
+    require(log2Up(conf.nxpr) == 5)
     
     val status = new Status().asOutput
     val ptbr = UFix(OUTPUT, PADDR_BITS)
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 27a79063..93e54cc2 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -21,7 +21,7 @@ class HostIO(val w: Int) extends Bundle
 class PCRReq extends Bundle
 {
   val rw = Bool()
-  val addr = Bits(width = 6)
+  val addr = Bits(width = 5)
   val data = Bits(width = 64)
 }
 
@@ -237,6 +237,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
     }
   }
 
+  val scr_addr = addr(log2Up(nSCR)-1, 0)
   val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)}
   for (i <- 0 until scr_rdata.size)
     scr_rdata(i) := io.scr.rdata(i)
@@ -245,10 +246,10 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
 
   io.scr.wen := false
   io.scr.wdata := pcr_wdata
-  io.scr.waddr := pcr_addr.toUFix
+  io.scr.waddr := scr_addr.toUFix
   when (state === state_pcr_req && pcr_coreid === Fix(-1)) {
     io.scr.wen := cmd === cmd_writecr
-    pcrReadData := scr_rdata(pcr_addr)
+    pcrReadData := scr_rdata(scr_addr)
     state := state_tx
   }