riscv/rocket-chip
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timer interrupt fixes

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This commit is contained in:
Rimas Avizienis 2011-11-13 00:32:08 -08:00
parent 345f950eff
commit 44419511b7
2 changed files with 4 additions and 6 deletions
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9
rocket/src/main/scala/ctrl.scala
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@ -58,6 +58,7 @@ class ioCtrlDpath extends Bundle()
val sboard_clr0a = UFix(5, 'input); val sboard_clr0a = UFix(5, 'input);
val sboard_clr1 = Bool('input); val sboard_clr1 = Bool('input);
val sboard_clr1a = UFix(5, 'input); val sboard_clr1a = UFix(5, 'input);
val timer_int = Bool('input);
} }
class ioCtrlAll extends Bundle() class ioCtrlAll extends Bundle()
@ -69,13 +70,11 @@ class ioCtrlAll extends Bundle()
val host = new ioHost(List("start")); val host = new ioHost(List("start"));
val dtlb_busy = Bool('input); val dtlb_busy = Bool('input);
val dtlb_miss = Bool('input); val dtlb_miss = Bool('input);
// val itlb_miss = Bool('input);
val xcpt_dtlb_ld = Bool('input); val xcpt_dtlb_ld = Bool('input);
val xcpt_dtlb_st = Bool('input); val xcpt_dtlb_st = Bool('input);
val xcpt_itlb = Bool('input); val xcpt_itlb = Bool('input);
val xcpt_ma_ld = Bool('input); val xcpt_ma_ld = Bool('input);
val xcpt_ma_st = Bool('input); val xcpt_ma_st = Bool('input);
val timer_int = Bool('input);
} }
class rocketCtrl extends Component class rocketCtrl extends Component
@ -332,7 +331,6 @@ class rocketCtrl extends Component
val jr_taken = (ex_reg_br_type === BR_JR); val jr_taken = (ex_reg_br_type === BR_JR);
val j_taken = (ex_reg_br_type === BR_J); val j_taken = (ex_reg_br_type === BR_J);
// io.dmem.req_val := ex_reg_mem_val;
io.dmem.req_val := ex_reg_mem_val && ~io.dpath.killx; io.dmem.req_val := ex_reg_mem_val && ~io.dpath.killx;
io.dmem.req_cmd := ex_reg_mem_cmd; io.dmem.req_cmd := ex_reg_mem_cmd;
io.dmem.req_type := ex_reg_mem_type; io.dmem.req_type := ex_reg_mem_type;
@ -384,7 +382,7 @@ class rocketCtrl extends Component
// exception handling // exception handling
// FIXME: verify PC in MEM stage points to valid, restartable instruction // FIXME: verify PC in MEM stage points to valid, restartable instruction
val interrupt = io.dpath.status(SR_ET).toBool && io.dpath.status(15).toBool && io.timer_int; val interrupt = io.dpath.status(SR_ET).toBool && io.dpath.status(15).toBool && io.dpath.timer_int;
val interrupt_cause = UFix(0x17, 5); val interrupt_cause = UFix(0x17, 5);
val mem_exception = val mem_exception =
@ -421,9 +419,9 @@ class rocketCtrl extends Component
// replay execute stage PC when the D$ is blocked, when the D$ misses, and for privileged instructions // replay execute stage PC when the D$ is blocked, when the D$ misses, and for privileged instructions
val replay_ex = (ex_reg_mem_val && !io.dmem.req_rdy) || io.dmem.resp_miss || mem_reg_privileged; val replay_ex = (ex_reg_mem_val && !io.dmem.req_rdy) || io.dmem.resp_miss || mem_reg_privileged;
// replay mem stage PC on a DTLB miss // replay mem stage PC on a DTLB miss
val replay_mem = io.dtlb_miss; val replay_mem = io.dtlb_miss;
// val replay_mem = Bool(false);
val kill_ex = replay_ex || replay_mem; val kill_ex = replay_ex || replay_mem;
val kill_mem = mem_exception || replay_mem; val kill_mem = mem_exception || replay_mem;
@ -525,7 +523,6 @@ class rocketCtrl extends Component
io.dpath.stalld := ctrl_stalld.toBool; io.dpath.stalld := ctrl_stalld.toBool;
// io.dpath.killf := take_pc | io.itlb_miss | ~io.imem.resp_val;
io.dpath.killf := take_pc | ~io.imem.resp_val; io.dpath.killf := take_pc | ~io.imem.resp_val;
io.dpath.killd := ctrl_killd.toBool; io.dpath.killd := ctrl_killd.toBool;
io.dpath.killx := kill_ex.toBool; io.dpath.killx := kill_ex.toBool;

1
rocket/src/main/scala/dpath.scala
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@ -355,6 +355,7 @@ class rocketDpath extends Component
pcr.io.host.from ^^ io.host.from; pcr.io.host.from ^^ io.host.from;
pcr.io.host.to ^^ io.host.to; pcr.io.host.to ^^ io.host.to;
io.ctrl.timer_int := pcr.io.timer_int;
io.ctrl.status := pcr.io.status; io.ctrl.status := pcr.io.status;
io.ptbr := pcr.io.ptbr; io.ptbr := pcr.io.ptbr;
io.debug.error_mode := pcr.io.debug.error_mode; io.debug.error_mode := pcr.io.debug.error_mode;