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Merge pull request #727 from ucb-bar/fix-axi2tl-timeout

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Wes's fix for AXI2TL timeout when writes backed up
This commit is contained in:
Yunsup Lee 2017-05-04 01:42:48 -07:00 committed by GitHub
commit 431e726c29
2 changed files with 15 additions and 12 deletions
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7
src/main/scala/rocket/ICache.scala
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@ -47,6 +47,7 @@ class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = true, executable = true,
supportsPutFull = TransferSizes(1, wordBytes), supportsPutFull = TransferSizes(1, wordBytes),
supportsPutPartial = TransferSizes(1, wordBytes),
supportsGet = TransferSizes(1, wordBytes), supportsGet = TransferSizes(1, wordBytes),
fifoId = Some(0))), // requests handled in FIFO order fifoId = Some(0))), // requests handled in FIFO order
beatBytes = wordBytes, beatBytes = wordBytes,
@ -226,7 +227,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
io.resp.valid := s2_valid && s2_hit && !s2_disparity io.resp.valid := s2_valid && s2_hit && !s2_disparity
tl_in.map { tl => tl_in.map { tl =>
tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid) val respValid = RegInit(false.B)
tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid)
val s1_a = RegEnable(tl.a.bits, s0_slaveValid) val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
when (s0_slaveValid) { when (s0_slaveValid) {
val a = tl.a.bits val a = tl.a.bits
@ -243,7 +245,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr) assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
when (!(tl.a.valid || s1_slaveValid || s2_slaveValid) when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) { && s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) {
// handle correctable errors on CPU accesses to the scratchpad. // handle correctable errors on CPU accesses to the scratchpad.
// if there is an in-flight slave-port access to the scratchpad, // if there is an in-flight slave-port access to the scratchpad,
@ -254,7 +256,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
s1s3_slaveAddr := Cat(OHToUInt(s2_tag_hit), io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0)) s1s3_slaveAddr := Cat(OHToUInt(s2_tag_hit), io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0))
} }
val respValid = RegInit(false.B)
respValid := s2_slaveValid || (respValid && !tl.d.ready) respValid := s2_slaveValid || (respValid && !tl.d.ready)
when (s2_slaveValid) { when (s2_slaveValid) {
when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true } when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }

20
src/main/scala/uncore/axi4/ToTL.scala
View File

@ -50,9 +50,11 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) => ((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
val numIds = edgeIn.master.endId val numIds = edgeIn.master.endId
val beatBytes = edgeOut.manager.beatBytes val beatBytes = edgeOut.manager.beatBytes
val countBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1 val beatCountBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
val maxFlight = edgeIn.master.masters.map(_.maxFlight.get).max val maxFlight = edgeIn.master.masters.map(_.maxFlight.get).max
val addedBits = log2Ceil(maxFlight) + 1 val logFlight = log2Ceil(maxFlight)
val txnCountBits = log2Ceil(maxFlight+1) // wrap-around must not block b_allow
val addedBits = logFlight + 1 // +1 for read vs. write source ID
require (edgeIn.master.userBits == 0, "AXI4 user bits cannot be transported by TL") require (edgeIn.master.userBits == 0, "AXI4 user bits cannot be transported by TL")
require (edgeIn.master.masters(0).aligned) require (edgeIn.master.masters(0).aligned)
@ -72,10 +74,10 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
val r_size = OH1ToUInt(r_size1) val r_size = OH1ToUInt(r_size1)
val r_ok = edgeOut.manager.supportsGetSafe(in.ar.bits.addr, r_size) val r_ok = edgeOut.manager.supportsGetSafe(in.ar.bits.addr, r_size)
val r_addr = Mux(r_ok, in.ar.bits.addr, UInt(error) | in.ar.bits.addr(log2Up(beatBytes)-1, 0)) val r_addr = Mux(r_ok, in.ar.bits.addr, UInt(error) | in.ar.bits.addr(log2Up(beatBytes)-1, 0))
val r_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) }) val r_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
val r_id = Cat(in.ar.bits.id, r_count(in.ar.bits.id), UInt(0, width=1)) val r_id = Cat(in.ar.bits.id, r_count(in.ar.bits.id)(logFlight-1,0), UInt(0, width=1))
assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned
in.ar.ready := r_out.ready in.ar.ready := r_out.ready
r_out.valid := in.ar.valid r_out.valid := in.ar.valid
r_out.bits := edgeOut.Get(r_id, r_addr, r_size)._2 r_out.bits := edgeOut.Get(r_id, r_addr, r_size)._2
@ -90,10 +92,10 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
val w_size = OH1ToUInt(w_size1) val w_size = OH1ToUInt(w_size1)
val w_ok = edgeOut.manager.supportsPutPartialSafe(in.aw.bits.addr, w_size) val w_ok = edgeOut.manager.supportsPutPartialSafe(in.aw.bits.addr, w_size)
val w_addr = Mux(w_ok, in.aw.bits.addr, UInt(error) | in.aw.bits.addr(log2Up(beatBytes)-1, 0)) val w_addr = Mux(w_ok, in.aw.bits.addr, UInt(error) | in.aw.bits.addr(log2Up(beatBytes)-1, 0))
val w_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) }) val w_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
val w_id = Cat(in.aw.bits.id, w_count(in.aw.bits.id), UInt(1, width=1)) val w_id = Cat(in.aw.bits.id, w_count(in.aw.bits.id)(logFlight-1,0), UInt(1, width=1))
assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned
assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned
in.aw.ready := w_out.ready && in.w.valid && in.w.bits.last in.aw.ready := w_out.ready && in.w.valid && in.w.bits.last
in.w.ready := w_out.ready && in.aw.valid in.w.ready := w_out.ready && in.aw.valid
@ -134,7 +136,7 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
// We need to prevent sending B valid before the last W beat is accepted // We need to prevent sending B valid before the last W beat is accepted
// TileLink allows early acknowledgement of a write burst, but AXI does not. // TileLink allows early acknowledgement of a write burst, but AXI does not.
val b_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) }) val b_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
val b_allow = b_count(in.b.bits.id) =/= w_count(in.b.bits.id) val b_allow = b_count(in.b.bits.id) =/= w_count(in.b.bits.id)
val b_sel = UIntToOH(in.b.bits.id, numIds) val b_sel = UIntToOH(in.b.bits.id, numIds)