riscv/rocket-chip
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debug: Breaking change until FESVR is updated as well.

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* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
This commit is contained in:
Megan Wachs
2017-03-27 21:19:08 -07:00
parent 43804726ac
commit 42ca597478
10 changed files with 1477 additions and 1019 deletions
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8
src/main/scala/coreplex/RocketTiles.scala
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@ -33,11 +33,8 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
}
// Hack debug interrupt into a node (future debug module should use diplomacy)
val debugNode = IntInternalInputNode(IntSourcePortSimple())
val intBar = LazyModule(new IntXbar)
intBar.intnode := debugNode
intBar.intnode := debug.intnode // Debug Interrupt
intBar.intnode := clint.intnode // msip+mtip
intBar.intnode := plic.intnode // meip
if (c.core.useVM) intBar.intnode := plic.intnode // seip
@ -56,7 +53,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
// leave clock as default (simpler for hierarchical PnR)
wrapper.module.io.hartid := UInt(i)
wrapper.module.io.resetVector := io.resetVector
debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
}
}
case Asynchronous(depth, sync) => {
@ -75,7 +71,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
wrapper.module.reset := io.tcrs(i).reset
wrapper.module.io.hartid := UInt(i)
wrapper.module.io.resetVector := io.resetVector
debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
}
}
case Rational => {
@ -94,7 +89,6 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
wrapper.module.reset := io.tcrs(i).reset
wrapper.module.io.hartid := UInt(i)
wrapper.module.io.resetVector := io.resetVector
debugNode.bundleOut(0)(0) := debug.module.io.debugInterrupts(i)
}
}
}