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debug: Breaking change until FESVR is updated as well.

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* Replace v11 Debug Module with v13 module.
* Correct all instantiating interfaces.
* Rename "Debug Bus" to "DMI" (Debug
  Module Interface)
* Use Diplomacy interrupts for DebugInterrupt
* Seperate device for TLDebugROM
This commit is contained in:
Megan Wachs
2017-03-27 21:19:08 -07:00
parent 43804726ac
commit 42ca597478
10 changed files with 1477 additions and 1019 deletions
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2
src/main/scala/coreplex/Configs.scala
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@ -22,7 +22,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => Synchronous
case RocketTilesKey => Nil
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case DMKey => new DefaultDebugModuleConfig(site(XLen))
case NTiles => site(RocketTilesKey).size
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth