riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Secondary miss param

Browse Source
This commit is contained in:
Henry Cook 2015-03-17 22:53:50 -07:00
parent b364d387de
commit 42aa4aa8ca
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
uncore/src/main/scala/cache.scala
View File

@ -10,6 +10,8 @@ case object RowBits extends Field[Int]
case object Replacer extends Field[() => ReplacementPolicy] case object Replacer extends Field[() => ReplacementPolicy]
case object AmoAluOperandBits extends Field[Int] case object AmoAluOperandBits extends Field[Int]
case object L2DirectoryRepresentation extends Field[DirectoryRepresentation] case object L2DirectoryRepresentation extends Field[DirectoryRepresentation]
case object NPrimaryMisses extends Field[Int]
case object NSecondaryMisses extends Field[Int]
case object CacheBlockBytes extends Field[Int] case object CacheBlockBytes extends Field[Int]
case object CacheBlockOffsetBits extends Field[Int] case object CacheBlockOffsetBits extends Field[Int]
@ -171,7 +173,7 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
val amoAluOperandBits = params(AmoAluOperandBits) val amoAluOperandBits = params(AmoAluOperandBits)
require(amoAluOperandBits <= innerDataBits) require(amoAluOperandBits <= innerDataBits)
require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
val nSecondaryMisses = 4 val nSecondaryMisses = params(NSecondaryMisses)
} }
abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters