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tilelink2 RegisterCrossing: Queues go from RV to Irrevocable

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AsyncQueue is still a Queue.
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Wesley W. Terpstra 2016-10-02 00:35:57 -07:00 committed by Andrew Waterman
parent 02f89fb530
commit 422e6357a4
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/uncore/tilelink2/RegisterCrossing.scala
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@ -3,7 +3,7 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.{Irrevocable, IrrevocableIO} import chisel3.util.{Irrevocable}
import util.{AsyncResetRegVec, AsyncQueue, AsyncScope} import util.{AsyncResetRegVec, AsyncQueue, AsyncScope}
// A very simple flow control state machine, run in the specified clock domain // A very simple flow control state machine, run in the specified clock domain
@ -25,7 +25,7 @@ class BusyRegisterCrossing(clock: Clock, reset: Bool)
// RegField should support connecting to one of these // RegField should support connecting to one of these
class RegisterWriteIO[T <: Data](gen: T) extends Bundle { class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
val request = Irrevocable(gen).flip() val request = Decoupled(gen).flip()
val response = Irrevocable(Bool()) // ignore .bits val response = Irrevocable(Bool()) // ignore .bits
} }
@ -85,7 +85,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
// RegField should support connecting to one of these // RegField should support connecting to one of these
class RegisterReadIO[T <: Data](gen: T) extends Bundle { class RegisterReadIO[T <: Data](gen: T) extends Bundle {
val request = Irrevocable(Bool()).flip() // ignore .bits val request = Decoupled(Bool()).flip() // ignore .bits
val response = Irrevocable(gen) val response = Irrevocable(gen)
} }