diff --git a/src/main/scala/uncore/tilelink2/RegisterCrossing.scala b/src/main/scala/uncore/tilelink2/RegisterCrossing.scala
index b908baf4..85ec94f8 100644
--- a/src/main/scala/uncore/tilelink2/RegisterCrossing.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterCrossing.scala
@@ -3,7 +3,7 @@
 package uncore.tilelink2
 
 import Chisel._
-import chisel3.util.{Irrevocable, IrrevocableIO}
+import chisel3.util.{Irrevocable}
 import util.{AsyncResetRegVec, AsyncQueue, AsyncScope}
 
 // A very simple flow control state machine, run in the specified clock domain
@@ -25,7 +25,7 @@ class BusyRegisterCrossing(clock: Clock, reset: Bool)
 
 // RegField should support connecting to one of these
 class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
-  val request  = Irrevocable(gen).flip()
+  val request  = Decoupled(gen).flip()
   val response = Irrevocable(Bool()) // ignore .bits
 }
 
@@ -85,7 +85,7 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
 
 // RegField should support connecting to one of these
 class RegisterReadIO[T <: Data](gen: T) extends Bundle {
-  val request  = Irrevocable(Bool()).flip() // ignore .bits
+  val request  = Decoupled(Bool()).flip() // ignore .bits
   val response = Irrevocable(gen)
 }