Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink

uncore/src/package.scala

@@ -1,6 +1,9 @@
 package object uncore {
 import Chisel._
 
+//TODO: Remove these Networking classes from the package object once Scala bug
+//SI-3439 is resolved.
+
 case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
 
 class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
@@ -22,14 +25,21 @@ class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfi
     val out = Vec(conf.nEndpoints) { (new BasicCrossbarIO) { data } }
   }
 
-  for(i <- 0 until conf.nEndpoints) {
+  val rdyVecs = List.fill(conf.nEndpoints)(Vec(conf.nEndpoints){Bool()})
+
+  io.out.zip(rdyVecs).zipWithIndex.map{ case ((out, rdys), i) => {
     val rrarb = new RRArbiter(conf.nEndpoints)(data)
-    (rrarb.io.in, io.in).zipped.map( (arb, io) => {
+    (rrarb.io.in, io.in, rdys).zipped.map{ case (arb, in, rdy) => {
-      arb.valid := io.valid && (io.header.dst === UFix(i)) 
+      arb.valid := in.valid && (in.header.dst === UFix(i)) 
-      arb.bits := io.bits
+      arb.bits := in.bits
-      io.ready := arb.ready
+      rdy := arb.ready && (in.header.dst === UFix(i))
-    })
+    }}
-    io.out(i) <> rrarb.io.out
+    out <> rrarb.io.out
+    out.header.src := rrarb.io.chosen.toUFix
+    out.header.dst := UFix(i)
+  }}
+  for(i <- 0 until conf.nEndpoints) {
+    io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_)
   }
 }
 
@@ -53,7 +63,7 @@ abstract class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalN
 class TileIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(conf)
 class HubIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends LogicalNetworkIO()(data)(conf){flip()}
 
-class TileLink(implicit conf: LogicalNetworkConfiguration) extends Bundle { 
+class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { 
   val xact_init      = (new TileIO) { new TransactionInit }
   val xact_init_data = (new TileIO) { new TransactionInitData }
   val xact_abort     = (new HubIO)  { new TransactionAbort }
@@ -62,7 +72,6 @@ class TileLink(implicit conf: LogicalNetworkConfiguration) extends Bundle {
   val probe_rep_data = (new TileIO) { new ProbeReplyData }
   val xact_rep       = (new HubIO)  { new TransactionReply }
   val xact_finish    = (new TileIO) { new TransactionFinish }
-  val incoherent     = Bool(OUTPUT)
+  override def clone = { new TileLinkIO().asInstanceOf[this.type] }
-  override def clone = { new TileLink().asInstanceOf[this.type] }
 }
 }

uncore/src/uncore.scala

@@ -225,9 +225,47 @@ class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Com
 
 case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConfiguration)
 
+class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
+  val io = new Bundle {
+    val net = (new TileLinkIO).flip
+    val hub = Vec(conf.nTiles) { new TileLinkIO }
+  }
+
+  val netTileProducedSubBundles = io.net.getClass.getMethods.filter( x =>
+    classOf[TileIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
+      m.invoke(io.net).asInstanceOf[TileIO[Data]] } 
+  val netHubProducedSubBundles  = io.net.getClass.getMethods.filter( x =>
+    classOf[HubIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
+      m.invoke(io.net).asInstanceOf[HubIO[Data]] }
+
+  val hubTileProducedSubBundles = io.hub.map{ io => { 
+    io.getClass.getMethods.filter( x =>
+      classOf[TileIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
+        m.invoke(io).asInstanceOf[TileIO[Data]] }}}.transpose
+  val hubHubProducedSubBundles = io.hub.map{ io => {
+    io.getClass.getMethods.filter( x =>
+      classOf[HubIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
+        m.invoke(io).asInstanceOf[HubIO[Data]] }}}.transpose
+
+  hubHubProducedSubBundles.zip(netHubProducedSubBundles).foreach{ case(hub, net) => {
+    net.header.src := UFix(0)
+    net.header.dst := Vec(hub.map(_.valid)){Bool()}.indexWhere{s: Bool => s}
+    net.valid := hub.map(_.valid).fold(Bool(false))(_||_)
+    net.bits := hub(0).bits
+    hub.foreach( _.ready := net.ready) 
+  }}
+  hubTileProducedSubBundles.zip(netTileProducedSubBundles).foreach{ case(hub, net) => {
+    hub.foreach(_.header := net.header)
+    hub.zipWithIndex.foreach{ case(h,i) => h.valid := (net.header.src === UFix(i)) && net.valid }
+    hub.foreach(_.bits := net.bits)
+    net.ready := hub.map(_.ready).fold(Bool(false))(_||_)
+  }}
+}
+
 abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
   val io = new Bundle {
-    val tiles = Vec(conf.nTiles) { new TileLink }.flip
+    val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
+    val incoherent = Vec(conf.nTiles) { Bool() }.asInput
     val mem = new ioMem
   }
 }
@@ -295,7 +333,7 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
     t.p_data.valid        := p_data_valid_arr(i)
     t.p_rep_cnt_dec       := p_rep_cnt_dec_arr(i).toBits
     t.p_req_cnt_inc       := p_req_cnt_inc_arr(i).toBits
-    t.tile_incoherent     := (Vec(io.tiles.map(_.incoherent)) { Bool() }).toBits
+    t.tile_incoherent     := io.incoherent.toBits
     t.sent_x_rep_ack      := sent_x_rep_ack_arr(i)
     do_free_arr(i)        := Bool(false)
     sent_x_rep_ack_arr(i) := Bool(false)