riscv/rocket-chip
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Conflicts:
	rocket
	uncore
This commit is contained in:
Henry Cook 2014-09-06 06:59:14 -07:00
commit 4126678c9d
12 changed files with 369 additions and 387 deletions
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6
Makefrag
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@ -22,7 +22,7 @@ timeout_cycles = 100000000
# VLSI Backend
$(generated_dir)/$(MODEL).v: $(chisel_srcs)
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend rocketchip.RocketChipBackend --targetDir $(generated_dir) --noInlineMem"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend rocketchip.RocketChipBackend --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.DefaultVLSIConfig"
cd $(generated_dir) && \
if [ -a $(MODEL).conf ]; then \
sed -i 's*^*$(vlsi_mem_gen) *' $(MODEL).conf && \
@ -32,13 +32,13 @@ $(generated_dir)/$(MODEL).v: $(chisel_srcs)
# FPGA Backend
$(generated_dir)/$(FPGAMODEL).v: $(chisel_srcs)
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(FPGAMODEL) --backend fpga --targetDir $(generated_dir)"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(FPGAMODEL) --backend fpga --targetDir $(generated_dir) --configInstance rocketchip.DefaultFPGAConfig"
$(generated_dir)/$(FPGAMODEL)Mem.v: $(generated_dir)/$(FPGAMODEL).conf $(mem_gen)
$(mem_gen) $(generated_dir)/$(FPGAMODEL).conf > $(generated_dir)/$(FPGAMODEL)Mem.v
$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.DefaultVLSIConfig"
#--------------------------------------------------------------------
# DRAMSim2

2
chisel

@ -1 +1 @@
Subproject commit c04dd5fae887d21a82ffbcbf063388604d7a5a3d
Subproject commit 30ff8ebf6f2ff0583276b19ed9fa08295c8957d1

8
emulator/Makefile
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@ -3,6 +3,8 @@ all: emulator
base_dir = $(abspath ..)
sim_dir = .
output_dir = $(sim_dir)/output
PROJECT = rocketchip
CONFIG = DefaultCPPConfig
include $(base_dir)/Makefrag
@ -16,14 +18,14 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --configInstance $(PROJECT).$(CONFIG) --targetDir emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).h: $(chisel_srcs)
cd $(base_dir) && $(SBT) "project rocketchip" "elaborate $(CHISEL_ARGS)"
cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS)"
generated-src-debug/$(MODEL).h: $(chisel_srcs)
cd $(base_dir) && $(SBT) "project rocketchip" "elaborate $(CHISEL_ARGS_DEBUG)"
cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS_DEBUG)"
$(MODEL).o: %.o: generated-src/%.h
$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))

2
hardfloat

@ -1 +1 @@
Subproject commit d5b680d9404988c54b3a2eeeb021bd3ff662e0cd
Subproject commit 1c8a6e6815eadebc1592c65e10a2ba87ecabb3c6

2
riscv-tools

@ -1 +1 @@
Subproject commit 94d919625a75b1d3087f16c1b346cee3c2fb45a8
Subproject commit 26f1c354253a2d4ca274314b3784bf78d2512498

2
rocket

@ -1 +1 @@
Subproject commit 03adcd4a267e3fbe24af9fd05801bde2eb182ed9
Subproject commit 15e0d48a614db7b44eebb830175f759a0eb0eaf1

177
src/main/scala/PublicConfigs.scala Normal file
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@ -0,0 +1,177 @@
package rocketchip
import Chisel._
import uncore._
import rocket._
import rocket.Util._
class DefaultConfig extends ChiselConfig {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match {
//HTIF Parameters
case HTIFWidth => 16
case HTIFNSCR => 64
case HTIFOffsetBits => site(CacheBlockOffsetBits)
case HTIFNCores => site(NTiles)
//Memory Parameters
case PAddrBits => 32
case VAddrBits => 43
case PgIdxBits => 13
case ASIdBits => 7
case PermBits => 6
case PPNBits => site(PAddrBits) - site(PgIdxBits)
case VPNBits => site(VAddrBits) - site(PgIdxBits)
case MIFTagBits => 5
case MIFDataBits => 128
case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case MIFDataBeats => site(TLDataBits)/site(MIFDataBits)
//Params used by all caches
case ECCCode => None
case WordBits => site(XprLen)
case Replacer => () => new RandomReplacement(site(NWays))
case BlockOffBits => site(CacheName) match {
case "L1I" | "L1D" => log2Up(site(TLDataBits)/8)
case "L2" => 0
}
case NSets => site(CacheName) match {
case "L1I" => 128
case "L1D" => Knob("L1D_SETS") //128
case "L2" => 512
}
case NWays => site(CacheName) match {
case "L1I" => 2
case "L1D" => Knob("L1D_WAYS") //4
case "L2" => 8
}
case RowBits => site(CacheName) match {
case "L1I" => 4*site(CoreInstBits)
case "L1D" => 2*site(CoreDataBits)
case "L2" => site(TLDataBits)
}
//L1InstCache
case NITLBEntries => 8
case NBTBEntries => 62
case NRAS => 2
//L1DataCache
case NDTLBEntries => 8
case StoreDataQueueDepth => 17
case ReplayQueueDepth => 16
case NMSHRs => Knob("L1D_MSHRS")
case LRSCCycles => 32
//L2CacheParams
case NReleaseTransactors => Knob("L2_REL_XACTS")
case NAcquireTransactors => Knob("L2_ACQ_XACTS")
case NClients => site(NTiles) + 1
//Tile Constants
case BuildRoCC => None
case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1)
case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3)
//Rocket Core Constants
case RetireWidth => 1
case UseVM => true
case FastLoadWord => true
case FastLoadByte => false
case FastMulDiv => true
case XprLen => 64
case NMultXpr => 32
case BuildFPU => Some(() => new FPU)
case SFMALatency => 2
case DFMALatency => 3
case CoreInstBits => 32
case CoreDataBits => site(XprLen)
case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
//Uncore Paramters
case LNMasters => site(NBanks)
case LNClients => site(NTiles)+1
case LNEndpoints => site(LNMasters) + site(LNClients)
case TLCoherence => site(Coherence)
case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
case TLDataBits => site(CacheBlockBytes)*8
case TLWriteMaskBits => 6
case TLWordAddrBits => 3
case TLAtomicOpBits => 4
case NTiles => Knob("NTILES")
case NBanks => Knob("NBANKS")
case BankIdLSB => 5
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
case UseBackupMemoryPort => true
case BuildDRAMSideLLC => (refill: Int) => {
if(site[Boolean]("USE_DRAMSIDE_LLC")) {
val tag = Mem(Bits(width = 152), 512, seqRead = true)
val data = Mem(Bits(width = 64), 4096, seqRead = true)
Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
refill_cycles=refill, tagLeaf=tag, dataLeaf=data))
} else { Module(new DRAMSideLLCNull(16, refill)) }
}
case BuildCoherenceMaster => (id: Int) => {
if(site[Boolean]("USE_L2_CACHE")) {
Module(new L2HellaCache(id), { case CacheName => "L2" })
} else {
Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
}
}
case Coherence => {
val dir = new FullRepresentation(site(NClients))
val enSharing = site[Boolean]("ENABLE_SHARING")
val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
if(enSharing) {
if(enCleanEx) new MESICoherence(dir)
else new MSICoherence(dir)
} else {
if(enCleanEx) new MEICoherence(dir)
else new MICoherence(dir)
}
}
case "ENABLE_SHARING" => true
case "ENABLE_CLEAN_EXCLUSIVE" => true
case "USE_DRAMSIDE_LLC" => true
case "USE_L2_CACHE" => false
}
}
override val knobValues:Any=>Any = {
case "NTILES" => 1
case "NBANKS" => 1
case "L2_REL_XACTS" => 1
case "L2_ACQ_XACTS" => 7
case "L1D_MSHRS" => 2
case "L1D_SETS" => 128
case "L1D_WAYS" => 4
}
}
class DefaultVLSIConfig extends DefaultConfig
class DefaultCPPConfig extends DefaultConfig
class FPGAConfig(default: ChiselConfig) extends ChiselConfig {
val topDefinitions:World.TopDefs = {
(pname,site,here) => pname match {
case NSets => site(CacheName) match {
case "L1I" => 64
case "L1D" => Knob("L1D_SETS")
}
case NWays => site(CacheName) match {
case "L1I" => 1
case "L1D" => Knob("L1D_WAYS")
}
case FastMulDiv => false
case NITLBEntries => 4
case NBTBEntries => 8
case NDTLBEntries => 4
case _ => default.topDefinitions(pname,site,here)
}
}
override val knobValues:Any=>Any = {
case "NTILES" => 1
case "NBANKS" => 1
case "L2_REL_XACTS" => 1
case "L2_ACQ_XACTS" => 7
case "L1D_MSHRS" => 2
case "L1D_SETS" => 64
case "L1D_WAYS" => 1
}
}
class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig)

285
src/main/scala/RocketChip.scala
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@ -5,184 +5,118 @@ import uncore._
import rocket._
import rocket.Util._
object DesignSpaceConstants {
val NTILES = 1
val NBANKS = 1
val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
val USE_DRAMSIDE_LLC = true
val HAS_FPU = true
val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 7
val NMSHRS = 2
case object NTiles extends Field[Int]
case object NBanks extends Field[Int]
case object BankIdLSB extends Field[Int]
case object CacheBlockBytes extends Field[Int]
case object CacheBlockOffsetBits extends Field[Int]
case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike]
case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent]
case object UseBackupMemoryPort extends Field[Boolean]
case object Coherence extends Field[CoherencePolicyWithUncached]
abstract trait TopLevelParameters extends UsesParameters {
val htifW = params(HTIFWidth)
val nTiles = params(NTiles)
val nBanks = params(NBanks)
val lsb = params(BankIdLSB)
val refillCycles = params(MIFDataBeats)
}
object MemoryConstants {
val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 //TODO: How configurable is this really?
val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
val PADDR_BITS = 32
val VADDR_BITS = 43
val PGIDX_BITS = 13
val ASID_BITS = 7
val PERM_BITS = 6
val MEM_TAG_BITS = 5
val MEM_DATA_BITS = 128
val MEM_ADDR_BITS = PADDR_BITS - OFFSET_BITS
val MEM_DATA_BEATS = 4
}
object TileLinkSizeConstants {
val WRITE_MASK_BITS = 6
val SUBWORD_ADDR_BITS = 3
val ATOMIC_OP_BITS = 4
}
import DesignSpaceConstants._
import MemoryConstants._
import TileLinkSizeConstants._
class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
class OuterMemorySystem extends Module with TopLevelParameters {
val io = new Bundle {
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip
val htif = (new TileLinkIO).flip
val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput
val mem = new MemIO
val mem_backup = new MemSerializedIO(htif_width)
val mem_backup = new MemSerializedIO(params(HTIFWidth))
val mem_backup_en = Bool(INPUT)
}
val refill_cycles = tl.dataBits/mif.dataBits
val (llc, masterEndpoints) = if(conf.useDRAMSideLLC) {
val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
val mes = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
(llc, mes)
} else {
val llc = Module(new DRAMSideLLCNull(16, refill_cycles))
val mes = (0 until ln.nMasters).map(i => Module(new L2HellaCache(i)))
(llc, mes)
}
// Create a simple NoC and points of coherence serialization
val net = Module(new RocketChipCrossbarNetwork)
val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
// Create a converter between TileLinkIO and MemIO
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
if(ln.nMasters > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
if(params(NBanks) > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {
conv.io.uncached <> masterEndpoints.head.io.outer
}
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles)
// Create a DRAM-side LLC
val llc = params(BuildDRAMSideLLC)(refillCycles)
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles)
conv.io.mem.resp <> llc.io.cpu.resp
// mux between main and backup memory ports
val mem_serdes = Module(new MemSerdes(htif_width))
val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
mem_cmdq.io.enq <> llc.io.mem.req_cmd
mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
val mem_dataq = Module(new Queue(new MemData, refill_cycles))
mem_dataq.io.enq <> llc.io.mem.req_data
mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
io.mem.req_data.bits := mem_dataq.io.deq.bits
mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
io.mem.resp.ready := Bool(true)
llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
io.mem_backup <> mem_serdes.io.narrow
// Create a SerDes for backup memory port
if(params(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup,
io.mem_backup_en, htifW)
} else {
io.mem <> llc.io.mem
}
}
case class UncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int, useDRAMSideLLC: Boolean)
class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
{
implicit val (tl, mif) = (conf.tl, conf.mif)
class Uncore extends Module with TopLevelParameters {
val io = new Bundle {
val host = new HostIO(htif_width)
val host = new HostIO
val mem = new MemIO
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
val mem_backup = new MemSerializedIO(htif_width)
val tiles = Vec.fill(nTiles){new TileLinkIO}.flip
val htif = Vec.fill(nTiles){new HTIFIO}.flip
val incoherent = Vec.fill(nTiles){Bool()}.asInput
val mem_backup = new MemSerializedIO(htifW)
val mem_backup_en = Bool(INPUT)
}
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
val outmemsys = Module(new OuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif
outmemsys.io.mem <> io.mem
outmemsys.io.mem_backup_en <> io.mem_backup_en
// Add networking headers and endpoint queues
def convertAddrToBank(addr: Bits): UInt = {
require(conf.bankIdLsb + log2Up(conf.nBanks) < conf.mif.addrBits, {println("Invalid bits for bank multiplexing.")})
addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
// Used to hash physical addresses to banks
require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits))
def addrToBank(addr: Bits): UInt = {
if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb)
else UInt(0)
}
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) =>
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _))
val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip
val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes
// Wire outer mem system to tiles and htif, adding
// networking headers and endpoint queues
(outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports
.zip(io.tiles :+ htif.io.mem) // Zip them with matching ports from clients
.zipWithIndex // Index them
.map { case ((outer, client), i) => // Then use the index and bank hash to
// overwrite the networking header
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _))
outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe)
}
outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput)
// pad out the HTIF using a divided clock
val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) })
hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63
hio.io.set_divisor.bits := htif.io.scr.wdata
htif.io.scr.rdata(63) := hio.io.divisor
hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid
hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits))
htif.io.host.out.ready := hio.io.out_fast.ready
outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
io.host.out.bits := hio.io.out_slow.bits
io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
io.host.in.ready := hio.io.in_slow.ready
outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits
htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
htif.io.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
io.host.clk := hio.io.clk_slow
io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk))
// Wire the htif to the memory port(s) and host interface
io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
htif.io.cpu <> io.htif
outmemsys.io.mem <> io.mem
if(params(UseBackupMemoryPort)) {
outmemsys.io.mem_backup_en := io.mem_backup_en
VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup,
io.mem_backup, io.host, io.mem_backup_en, htifW)
} else {
htif.io.host.out <> io.host.out
htif.io.host.in <> io.host.in
}
}
class TopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends Bundle {
val host = new HostIO(htifWidth)
class TopIO extends Bundle {
val host = new HostIO
val mem = new MemIO
}
class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) {
val mem_backup_en = Bool(INPUT)
val in_mem_ready = Bool(OUTPUT)
val in_mem_valid = Bool(INPUT)
@ -190,59 +124,14 @@ class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends To
val out_mem_valid = Bool(OUTPUT)
}
class Top extends Module with TopLevelParameters {
val io = new TopIO
class MemDessert extends Module {
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
val io = new MemDesserIO(HTIF_WIDTH)
val x = Module(new MemDesser(HTIF_WIDTH))
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}
val resetSigs = Vec.fill(nTiles){Bool()}
val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))))
val uncore = Module(new Uncore)
class Top extends Module {
val dir = new FullRepresentation(NTILES+1)
val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir)
else new MSICoherence(dir)
} else {
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir)
else new MICoherence(dir)
}
implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
implicit val tl = TileLinkConfiguration(co = co, ln = ln,
addrBits = as.paddrBits-OFFSET_BITS,
clientXactIdBits = log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS),
masterXactIdBits = 2*log2Up(NMSHRS*NTILES+1),
dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
writeMaskBits = WRITE_MASK_BITS,
wordAddrBits = SUBWORD_ADDR_BITS,
atomicOpBits = ATOMIC_OP_BITS)
implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as)
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = USE_DRAMSIDE_LLC)
val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2))
val dc = DCacheConfig(sets = 128, ways = 4,
tl = tl, as = as,
ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17,
reqtagbits = -1, databits = -1)
val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
val rc = RocketConfiguration(tl, as, ic, dc, fpu
//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
val io = new VLSITopIO(HTIF_WIDTH)
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new Uncore(HTIF_WIDTH))
for (i <- 0 until uc.nTiles) {
for (i <- 0 until nTiles) {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)
@ -254,20 +143,20 @@ class Top extends Module {
il := hl.reset
tile.io.host.id := UInt(i)
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req, 1)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1)
hl.ipi_req <> Queue(tile.io.host.ipi_req, 1)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1)
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
}
io.host <> uncore.io.host
io.mem <> uncore.io.mem
if(params(UseBackupMemoryPort)) {
uncore.io.mem_backup.resp.valid := io.in_mem_valid
io.out_mem_valid := uncore.io.mem_backup.req.valid
uncore.io.mem_backup.req.ready := io.out_mem_ready
io.mem_backup_en <> uncore.io.mem_backup_en
io.mem <> uncore.io.mem
}
}

153
src/main/scala/fpga.scala
View File

@ -1,155 +1,6 @@
package rocketchip
import Chisel._
import uncore._
import rocket._
import DesignSpaceConstants._
class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
extends Module {
implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif)
val io = new Bundle {
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val htif = (new TileLinkIO).flip
val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
val mem = new MemIO
}
val refill_cycles = tl.dataBits/mif.dataBits
val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16,
refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
val net = Module(new RocketChipCrossbarNetwork)
net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
if(ln.nMasters > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters))
arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {
conv.io.uncached <> masterEndpoints.head.io.outer
}
llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd)
llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles)
conv.io.mem.resp <> llc.io.cpu.resp
val mem_cmdq = Module(new Queue(new MemReqCmd, 2))
mem_cmdq.io.enq <> llc.io.mem.req_cmd
mem_cmdq.io.deq.ready := io.mem.req_cmd.ready
io.mem.req_cmd.valid := mem_cmdq.io.deq.valid
io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
val mem_dataq = Module(new Queue(new MemData, refill_cycles))
mem_dataq.io.enq <> llc.io.mem.req_data
mem_dataq.io.deq.ready := io.mem.req_data.ready
io.mem.req_data.valid := mem_dataq.io.deq.valid
io.mem.req_data.bits := mem_dataq.io.deq.bits
llc.io.mem.resp.valid := io.mem.resp.valid
io.mem.resp.ready := Bool(true)
llc.io.mem.resp.bits := io.mem.resp.bits
}
case class FPGAUncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nSCR: Int, offsetBits: Int)
class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration)
extends Module {
implicit val (tl, ln, mif) = (conf.tl, conf.tl.ln, conf.mif)
val io = new Bundle {
val host = new HostIO(htif_width)
val mem = new MemIO
val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
}
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif
outmemsys.io.mem <> io.mem
// Add networking headers and endpoint queues
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) =>
outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false))
outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false))
outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true))
client.grant <> Queue(outer.grant, 1, pipe = true)
client.probe <> Queue(outer.probe)
}
htif.io.host.out <> io.host.out
htif.io.host.in <> io.host.in
}
import MemoryConstants._
import TileLinkSizeConstants._
import MemoryConstants._
class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
class FPGATop extends Module {
val ntiles = 1
val nmshrs = 2
val htif_width = 16
val co = new MESICoherence(new FullRepresentation(ntiles+1))
implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1)
implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
implicit val tl = TileLinkConfiguration(co = co, ln = ln,
addrBits = as.paddrBits-OFFSET_BITS,
clientXactIdBits = log2Up(1+8),
masterXactIdBits = 2*log2Up(2*1+1),
dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
writeMaskBits = WRITE_MASK_BITS,
wordAddrBits = SUBWORD_ADDR_BITS,
atomicOpBits = ATOMIC_OP_BITS)
implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as)
implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS)
val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
val rc = RocketConfiguration(tl, as, ic, dc, fpu = None,
fastMulDiv = false)
val io = new FPGATopIO(htif_width)
val resetSigs = Vec.fill(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
val uncore = Module(new FPGAUncore(htif_width))
for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)
resetSigs(i) := hl.reset
val tile = tileList(i)
tile.io.tilelink <> tl
il := hl.reset
tile.io.host.id := UInt(i)
tile.io.host.reset := Reg(next=Reg(next=hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi_req <> Queue(tile.io.host.ipi_req)
tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
}
uncore.io.host <> io.host
uncore.io.mem <> io.mem
}
abstract class AXISlave extends Module {
val aw = 5
@ -163,7 +14,7 @@ abstract class AXISlave extends Module {
class Slave extends AXISlave
{
val top = Module(new FPGATop)
val top = Module(new Top)
val memw = top.io.mem.resp.bits.data.getWidth
val htifw = top.io.host.in.bits.getWidth
@ -202,7 +53,7 @@ class Slave extends AXISlave
// write cr1 -> mem.resp (nonblocking)
val in_count = Reg(init=UInt(0, log2Up(memw/dw)))
val rf_count = Reg(init=UInt(0, log2Up(CACHE_DATA_SIZE_IN_BYTES*8/memw)))
val rf_count = Reg(init=UInt(0, log2Up(params(CacheBlockBytes)*8/memw)))
require(memw % dw == 0 && isPow2(memw/dw))
val in_reg = Reg(top.io.mem.resp.bits.data)
top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw))

39
src/main/scala/network.scala
View File

@ -6,7 +6,7 @@ import scala.reflect._
import scala.reflect.runtime.universe._
object TileLinkHeaderOverwriter {
def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = {
val out = in.clone.asDirectionless
out.bits.payload := in.bits.payload
out.bits.header.src := UInt(clientId)
@ -15,29 +15,26 @@ object TileLinkHeaderOverwriter {
in.ready := out.ready
out
}
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = {
def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0))
out
}
}
class RocketChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
extends LogicalNetwork[TileLinkIO]()(conf.ln) {
implicit val (ln, co) = (conf.ln, conf.co)
class RocketChipCrossbarNetwork extends LogicalNetwork {
val io = new Bundle {
val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip}
val masters = Vec.fill(ln.nMasters){new TileLinkIO}
val clients = Vec.fill(params(LNClients)){(new TileLinkIO).flip}
val masters = Vec.fill(params(LNMasters)){new TileLinkIO}
}
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
val n = params(LNEndpoints)
// Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(new Acquire))
val relNet = Module(new BasicCrossbar(new Release))
val prbNet = Module(new BasicCrossbar(new Probe))
val gntNet = Module(new BasicCrossbar(new Grant))
val ackNet = Module(new BasicCrossbar(new Finish))
val acqNet = Module(new BasicCrossbar(n, new Acquire))
val relNet = Module(new BasicCrossbar(n, new Release))
val prbNet = Module(new BasicCrossbar(n, new Probe))
val gntNet = Module(new BasicCrossbar(n, new Grant))
val ackNet = Module(new BasicCrossbar(n, new Finish))
// Aliases for the various network IO bundle types
type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]]
@ -57,16 +54,16 @@ class RocketChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
}
def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
val out = DefaultFromCrossbarShim(in)
out.bits.header.src := in.bits.header.src - UInt(ln.nMasters)
out.bits.header.src := in.bits.header.src - UInt(params(LNMasters))
out
}
def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
val out = DefaultFromCrossbarShim(in)
out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters)
out.bits.header.dst := in.bits.header.dst - UInt(params(LNMasters))
out
}
def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = Decoupled(new PhysicalNetworkIO(in.bits.payload)).asDirectionless
val out = Decoupled(new PhysicalNetworkIO(n,in.bits.payload)).asDirectionless
out.bits.header := in.bits.header
out.bits.payload := in.bits.payload
out.valid := in.valid
@ -75,12 +72,12 @@ class RocketChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
}
def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters)
out.bits.header.dst := in.bits.header.dst + UInt(params(LNMasters))
out
}
def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.src := in.bits.header.src + UInt(ln.nMasters)
out.bits.header.src := in.bits.header.src + UInt(params(LNMasters))
out
}
@ -112,11 +109,11 @@ class RocketChipCrossbarNetwork(implicit conf: TileLinkConfiguration)
typeTag[T].tpe match{
case t if t <:< typeTag[ClientSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) }
}
case t if t <:< typeTag[MasterSourcedMessage].tpe => {
io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) }
}
case _ => require(false, "Unknown message sourcing.")
}

66
src/main/scala/vlsi.scala Normal file
View File

@ -0,0 +1,66 @@
package rocketchip
import Chisel._
import uncore._
class MemDessert extends Module {
val io = new MemDesserIO(params(HTIFWidth))
val x = Module(new MemDesser(params(HTIFWidth)))
io.narrow <> x.io.narrow
io.wide <> x.io.wide
}
object VLSIUtils {
def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO,
backup: MemSerializedIO, en: Bool, w: Int) {
val mem_serdes = Module(new MemSerdes(w))
val wide = mem_serdes.io.wide
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
mem.req_cmd.valid := llc.req_cmd.valid && !en
mem.req_cmd.bits := llc.req_cmd.bits
wide.req_cmd.valid := llc.req_cmd.valid && en
wide.req_cmd.bits := llc.req_cmd.bits
llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
mem.req_data.valid := llc.req_data.valid && !en
mem.req_data.bits := llc.req_data.bits
wide.req_data.valid := llc.req_data.valid && en
wide.req_data.bits := llc.req_data.bits
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
mem.resp.ready := Bool(true)
backup <> mem_serdes.io.narrow
}
def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO,
parent: MemSerializedIO, host: HostIO,
en: Bool, htifW: Int) {
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
hio.io.set_divisor.bits := htif.scr.wdata
htif.scr.rdata(63) := hio.io.divisor
hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
htif.host.out.ready := hio.io.out_fast.ready
child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
host.out.bits := hio.io.out_slow.bits
parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready)
val mem_backup_resp_valid = en && parent.resp.valid
hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid
hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits)
host.in.ready := hio.io.in_slow.ready
child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
child.resp.bits := hio.io.in_fast.bits
htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
htif.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
host.clk := hio.io.clk_slow
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
}
}

2
uncore

@ -1 +1 @@
Subproject commit cbe63ed21c0ee70dc4c4eb7e7b14a6d093159eb7
Subproject commit 5aff088b40d39a8e33549e22c10506589eeab42b