From 548cf16061f783cd8baa55819489c01aee7d1106 Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Tue, 11 Feb 2014 14:36:47 -0800 Subject: [PATCH 01/16] Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse --- Makefrag | 5 +++++ chisel | 2 +- riscv-tests | 2 +- src/main/scala/RocketChip.scala | 7 +++++-- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/Makefrag b/Makefrag index 7c92290f..beb8126b 100644 --- a/Makefrag +++ b/Makefrag @@ -14,6 +14,11 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS) src_path = src/main/scala +#DESIGN := design_dsize8_c20b273 +SRC := rocket/$(src_path)/*.scala hwacha/$(src_path)/*.scala /uncore/$(src_path)/*.scala $(src_path)/*.scala +PROJ := referencechip + + #-------------------------------------------------------------------- # Tests #-------------------------------------------------------------------- diff --git a/chisel b/chisel index ae1d1de8..fcb94b3e 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 +Subproject commit fcb94b3e4acdc005935f6af91a768a7ff96d971c diff --git a/riscv-tests b/riscv-tests index a4815615..0c98ef83 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit a481561500f43c8a022cfc0ba1695914e1df4d57 +Subproject commit 0c98ef833db1f6eead3bd9ad083d9408d2d8decb diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index deb400f7..2c7996cc 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -252,8 +252,11 @@ class Top extends Module { implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) - val dc = DCacheConfig(128, 4, ntlb = 8, - nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) + + val dsize = RangeParam("dsize",7,7,9) + val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) + //val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) + val rc = RocketConfiguration(tl, ic, dc, fpu = HAS_FPU) From cb14baab88a8049c747e821b5d01d8cc82b90b68 Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Fri, 28 Feb 2014 15:57:46 -0800 Subject: [PATCH 02/16] Reformatted hammer directory, added parent scripts to repo, as well as README. --- src/main/scala/RocketChip.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 772ddd46..26bcd2d5 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -251,9 +251,10 @@ class Top extends Module { implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) - val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) + val isize = RangeParam("i",7,7,9) + val ic = ICacheConfig(math.pow(2, isize.getValue).toInt, 2, ntlb = 8, nbtb = 38) - val dsize = RangeParam("dsize",7,7,9) + val dsize = RangeParam("d",7,7,9) val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) //val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) From 08d81d0892e0b2b5f0b173198367cdb1d20577a2 Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Fri, 1 Aug 2014 18:09:37 -0700 Subject: [PATCH 03/16] First cut at using new chisel parameters for toplevel parameters and fpu --- chisel | 2 +- emulator/Makefile | 8 ++- rocket | 2 +- src/main/scala/RocketChip.scala | 121 +++++++++++++++++--------------- src/main/scala/fpga.scala | 25 +++---- 5 files changed, 80 insertions(+), 78 deletions(-) diff --git a/chisel b/chisel index 54ad639f..e600be36 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 54ad639f11a6ac3459dad4d81e007b3712bd66ba +Subproject commit e600be365d8fc5a9a868ed40ad72489817e79b44 diff --git a/emulator/Makefile b/emulator/Makefile index fba9d352..4f27f61e 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -2,6 +2,8 @@ all: emulator base_dir = .. sim_dir = . +PROJECT = referencechip +CONFIG = DefaultCPPConfig include $(base_dir)/Makefrag @@ -15,14 +17,14 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) -CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src +CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src --configInstance $(PROJECT).$(CONFIG) CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala - cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)" + cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS)" generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala - cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)" + cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS_DEBUG)" $(MODEL).o: %.o: generated-src/%.h $(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) diff --git a/rocket b/rocket index fd9bea86..1b01778c 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit fd9bea861cf8cb83ff57c419f8a20964742baba5 +Subproject commit 1b01778c1743d779966829e0edfb904528ac472f diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index c22a8eb7..5eeed279 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -5,42 +5,48 @@ import uncore._ import rocket._ import rocket.Util._ -object DesignSpaceConstants { - val NTILES = 1 - val NBANKS = 1 - val HTIF_WIDTH = 16 - val ENABLE_SHARING = true - val ENABLE_CLEAN_EXCLUSIVE = true - val USE_DRAMSIDE_LLC = true - val HAS_FPU = true - val NL2_REL_XACTS = 1 - val NL2_ACQ_XACTS = 7 - val NMSHRS = 2 +class DefaultVLSIConfig extends DefaultConfig +class DefaultFPGAConfig extends DefaultConfig +class DefaultCPPConfig extends DefaultConfig +class DefaultConfig extends ChiselConfig { + val top:World.TopDefs = { + (pname,site,here) => pname match { + //DesignSpaceConstants + case "NTILES" => 1 + case "NBANKS" => 1 + case "HTIF_WIDTH" => 16 + case "ENABLE_SHARING" => true + case "ENABLE_CLEAN_EXCLUSIVE" => true + case "USE_DRAMSIDE_LLC" => true + case "NL2_REL_XACTS" => 1 + case "NL2_ACQ_XACTS" => 7 + case "NMSHRS" => 2 + //FPUConstants + case HasFPU => true + case FPUParams => Alter({ + case SFMALatency => 2 + case DFMALatency => 3 + }) + //MemoryConstants + case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 //TODO: How configurable is this really? + case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES")) + case "PADDR_BITS" => 32 + case "VADDR_BITS" => 43 + case "PGIDX_BITS" => 13 + case "ASID_BITS" => 7 + case "PERM_BITS" => 6 + case "MEM_TAG_BITS" => 5 + case "MEM_DATA_BITS" => 128 + case "MEM_ADDR_BITS" => here[Int]("PADDR_BITS") - here[Int]("OFFSET_BITS") + case "MEM_DATA_BEATS" => 4 + //TileLinkSizeConstants + case "WRITE_MASK_BITS" => 6 + case "SUBWORD_ADDR_BITS" => 3 + case "ATOMIC_OP_BITS" => 4 + } + } } -object MemoryConstants { - val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 //TODO: How configurable is this really? - val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES) - val PADDR_BITS = 32 - val VADDR_BITS = 43 - val PGIDX_BITS = 13 - val ASID_BITS = 7 - val PERM_BITS = 6 - val MEM_TAG_BITS = 5 - val MEM_DATA_BITS = 128 - val MEM_ADDR_BITS = PADDR_BITS - OFFSET_BITS - val MEM_DATA_BEATS = 4 -} - -object TileLinkSizeConstants { - val WRITE_MASK_BITS = 6 - val SUBWORD_ADDR_BITS = 3 - val ATOMIC_OP_BITS = 4 -} - -import DesignSpaceConstants._ -import MemoryConstants._ -import TileLinkSizeConstants._ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module { @@ -192,55 +198,54 @@ class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends To class MemDessert extends Module { - implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) - val io = new MemDesserIO(HTIF_WIDTH) - val x = Module(new MemDesser(HTIF_WIDTH)) + implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) + val io = new MemDesserIO(params[Int]("HTIF_WIDTH")) + val x = Module(new MemDesser(params[Int]("HTIF_WIDTH"))) io.narrow <> x.io.narrow io.wide <> x.io.wide } class Top extends Module { - val dir = new FullRepresentation(NTILES+1) - val co = if(ENABLE_SHARING) { - if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence(dir) + val dir = new FullRepresentation(params[Int]("NTILES")+1) + val co = if(params[Boolean]("ENABLE_SHARING")) { + if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir) else new MSICoherence(dir) } else { - if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence(dir) + if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir) else new MICoherence(dir) } - implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1) - implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) + implicit val ln = LogicalNetworkConfiguration(log2Up(params[Int]("NTILES"))+1, params[Int]("NBANKS"), params[Int]("NTILES")+1) + implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS")) implicit val tl = TileLinkConfiguration(co = co, ln = ln, - addrBits = as.paddrBits-OFFSET_BITS, - clientXactIdBits = log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), - masterXactIdBits = 2*log2Up(NMSHRS*NTILES+1), - dataBits = CACHE_DATA_SIZE_IN_BYTES*8, - writeMaskBits = WRITE_MASK_BITS, - wordAddrBits = SUBWORD_ADDR_BITS, - atomicOpBits = ATOMIC_OP_BITS) - implicit val l2 = L2CacheConfig(512, 8, 1, 1, NL2_REL_XACTS, NL2_ACQ_XACTS, tl, as) - implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS) - implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS, useDRAMSideLLC = USE_DRAMSIDE_LLC) + addrBits = as.paddrBits-params[Int]("OFFSET_BITS"), + clientXactIdBits = log2Up(params[Int]("NL2_REL_XACTS")+params[Int]("NL2_ACQ_XACTS")), + masterXactIdBits = 2*log2Up(params[Int]("NMSHRS")*params[Int]("NTILES")+1), + dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8, + writeMaskBits = params[Int]("WRITE_MASK_BITS"), + wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"), + atomicOpBits = params[Int]("ATOMIC_OP_BITS")) + implicit val l2 = L2CacheConfig(512, 8, 1, 1, params[Int]("NL2_REL_XACTS"), params[Int]("NL2_ACQ_XACTS"), tl, as) + implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) + implicit val uc = UncoreConfiguration(l2, tl, mif, params[Int]("NTILES"), params[Int]("NBANKS"), bankIdLsb = 5, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"), useDRAMSideLLC = params[Boolean]("USE_DRAMSIDE_LLC")) val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2)) val dc = DCacheConfig(sets = 128, ways = 4, tl = tl, as = as, - ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, + ntlb = 8, nmshr = params[Int]("NMSHRS"), nrpq = 16, nsdq = 17, reqtagbits = -1, databits = -1) val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None - val rc = RocketConfiguration(tl, as, ic, dc, fpu + val rc = RocketConfiguration(tl, as, ic, dc // rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) ) - val io = new VLSITopIO(HTIF_WIDTH) + val io = new VLSITopIO(params[Int]("HTIF_WIDTH")) val resetSigs = Vec.fill(uc.nTiles){Bool()} val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) - val uncore = Module(new Uncore(HTIF_WIDTH)) + val uncore = Module(new Uncore(params[Int]("HTIF_WIDTH"))) for (i <- 0 until uc.nTiles) { val hl = uncore.io.htif(i) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 7f4df49b..c2e24565 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -62,11 +62,6 @@ class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) htif.io.host.in <> io.host.in } -import MemoryConstants._ -import TileLinkSizeConstants._ - -import MemoryConstants._ - class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) class FPGATop extends Module { @@ -76,22 +71,22 @@ class FPGATop extends Module { val co = new MESICoherence(new FullRepresentation(ntiles+1)) implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) - implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS) + implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS")) implicit val tl = TileLinkConfiguration(co = co, ln = ln, - addrBits = as.paddrBits-OFFSET_BITS, + addrBits = as.paddrBits-params[Int]("OFFSET_BITS"), clientXactIdBits = log2Up(1+8), masterXactIdBits = 2*log2Up(2*1+1), - dataBits = CACHE_DATA_SIZE_IN_BYTES*8, - writeMaskBits = WRITE_MASK_BITS, - wordAddrBits = SUBWORD_ADDR_BITS, - atomicOpBits = ATOMIC_OP_BITS) + dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8, + writeMaskBits = params[Int]("WRITE_MASK_BITS"), + wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"), + atomicOpBits = params[Int]("ATOMIC_OP_BITS")) implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) - implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4) - implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = OFFSET_BITS) + implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) + implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS")) val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2)) val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1) - val rc = RocketConfiguration(tl, as, ic, dc, fpu = None, + val rc = RocketConfiguration(tl, as, ic, dc, fastMulDiv = false) val io = new FPGATopIO(htif_width) @@ -173,7 +168,7 @@ class Slave extends AXISlave // write cr1 -> mem.resp (nonblocking) val in_count = Reg(init=UInt(0, log2Up(memw/dw))) - val rf_count = Reg(init=UInt(0, log2Up(CACHE_DATA_SIZE_IN_BYTES*8/memw))) + val rf_count = Reg(init=UInt(0, log2Up(params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8/memw))) require(memw % dw == 0 && isPow2(memw/dw)) val in_reg = Reg(top.io.mem.resp.bits.data) top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw)) From 63bd0b9d2ad91378b456d3dffe06ee806f43f2c4 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 8 Aug 2014 12:27:47 -0700 Subject: [PATCH 04/16] Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed. --- rocket | 2 +- src/main/scala/RocketChip.scala | 296 ++++++++++++++++++++++---------- src/main/scala/fpga.scala | 49 +++--- src/main/scala/network.scala | 39 ++--- uncore | 2 +- 5 files changed, 245 insertions(+), 143 deletions(-) diff --git a/rocket b/rocket index 1b01778c..6beea1de 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 1b01778c1743d779966829e0edfb904528ac472f +Subproject commit 6beea1debbdd8115f45d02318210df624e67e9f8 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 5eeed279..5bfa8698 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -21,58 +21,196 @@ class DefaultConfig extends ChiselConfig { case "NL2_REL_XACTS" => 1 case "NL2_ACQ_XACTS" => 7 case "NMSHRS" => 2 - //FPUConstants - case HasFPU => true + //Coherence + case Coherence => { + val dir = new FullRepresentation(site[Int]("NTILES")+1) + if(site[Boolean]("ENABLE_SHARING")) { + if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir) + else new MSICoherence(dir) + } else { + if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir) + else new MICoherence(dir) + } + } + //Rocket Constants + // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC + case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) + // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc + case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) + case BuildRoCC => None + case RetireWidth => 1 + case UseVM => true + case FastLoadWord => true + case FastLoadByte => false + case FastMulDiv => true + case DcacheReqTagBits => 7 + log2Up(here(NDCachePorts)) + case XprLen => 64 + case NXpr => 32 + case NXprBits => log2Up(here(NXpr)) + case BuildFPU => Some(() => new FPU) case FPUParams => Alter({ case SFMALatency => 2 case DFMALatency => 3 }) + case RocketDCacheParams => Alter({ + //L1 Specific + case StoreDataQueueDepth => 17 + case ReplayQueueDepth => 16 + case NMSHRs => site[Int]("NMSHRS") + case NTLBEntries => 8 + case CoreReqTagBits => site(DcacheReqTagBits) + case CoreDataBits => site(XprLen) + case RowWords => 2 + case ECCCode => new IdentityCode + //From uncore/cache.scala + case NSets => 128 + case NWays => 4 + case IsDM => here(NWays) == 1 + case OffBits => log2Up(site(TLDataBits)) + case IdxBits => log2Up(here(NSets)) + case UntagBits => here(OffBits) + here(IdxBits) + case TagBits => here(PAddrBits) - here(UntagBits) + case WayBits => log2Up(here(NWays)) + case Replacer => () => new RandomReplacement(site(NWays)) + case RowBits => here(RowWords)*here(CoreDataBits) + case WordBits => here(CoreDataBits) + case RefillCycles => site(TLDataBits)/here(RowBits) + //Derived + case MaxAddrBits => math.max(site(PPNBits),site(VPNBits)+1) + site(PgIdxBits) + case CoreDataBytes => here(CoreDataBits)/8 + case WordOffBits => log2Up(here(CoreDataBytes)) + case RowBytes => here(RowWords)*here(CoreDataBytes) + case RowOffBits => log2Up(here(RowBytes)) + case DoNarrowRead => here(CoreDataBits)*here(NWays) % here(RowBits) == 0 + case EncDataBits => here(ECCCode).width(here(CoreDataBits)) + case EncRowBits => here(RowWords)*here(EncDataBits) + case LRSCCycles => 32 + }) + case RocketFrontendParams => Alter({ + case InstBytes => 4 + case RowBytes => 16 + case NTLBEntries => 8 + case ECCCode => new IdentityCode + //From uncore/cache.scala + case NSets => 128 + case NWays => 2 + case IsDM => here(NWays) == 1 + case OffBits => log2Up(site(TLDataBits)/8) + case IdxBits => log2Up(here(NSets)) + case UntagBits => here(OffBits) + here(IdxBits) + case TagBits => here(PAddrBits) - here(UntagBits) + case WayBits => log2Up(here(NWays)) + case Replacer => () => new RandomReplacement(site(NWays)) + case RowBits => here(RowBytes)*8 + case RefillCycles => site(TLDataBits)/here(RowBits) + case RowOffBits => log2Up(here(RowBytes)) + }) + case CoreBTBParams => Alter({ + case Entries => 62 + case NRAS => 2 + case MatchBits => site(PgIdxBits) + case Pages => ((1 max(log2Up(here(Entries))))+1)/2*2 + // control logic assumes 2 divides pages + case OpaqueBits => log2Up(here(Entries)) + case NBHT => 1 << log2Up(here(Entries)*2) + }) //MemoryConstants - case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 //TODO: How configurable is this really? + case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES")) - case "PADDR_BITS" => 32 - case "VADDR_BITS" => 43 - case "PGIDX_BITS" => 13 - case "ASID_BITS" => 7 - case "PERM_BITS" => 6 - case "MEM_TAG_BITS" => 5 - case "MEM_DATA_BITS" => 128 - case "MEM_ADDR_BITS" => here[Int]("PADDR_BITS") - here[Int]("OFFSET_BITS") - case "MEM_DATA_BEATS" => 4 - //TileLinkSizeConstants - case "WRITE_MASK_BITS" => 6 - case "SUBWORD_ADDR_BITS" => 3 - case "ATOMIC_OP_BITS" => 4 + case PAddrBits => 32 + case VAddrBits => 43 + case PgIdxBits => 13 + case ASIdBits => 7 + case PermBits => 6 + case PPNBits => here(PAddrBits) - here(PgIdxBits) + case VPNBits => here(VAddrBits) - here(PgIdxBits) + case MIFTagBits => 5 + case MIFDataBits => 128 + case MIFAddrBits => here(PAddrBits) - here[Int]("OFFSET_BITS") + case MIFDataBeats => 4 + //Uncore Constants + case TileLinkL1Params => Alter({ + case LNMasters => site[Int]("NBANKS") + case LNClients => site[Int]("NTILES")+1 + case LNEndpoints => here(LNMasters) + here(LNClients) + case TLCoherence => site(Coherence) + case TLAddrBits => site[Int]("PADDR_BITS") - site[Int]("OFFSET_BITS") + case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS")) + case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1) + case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8 + case TLWriteMaskBits => 6 + case TLWordAddrBits => 3 + case TLAtomicOpBits => 4 + }) + case L2HellaCacheParams => Alter({ + case NReleaseTransactors => site[Int]("NL2_REL_XACTS") + case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS") + case NTransactors => here(NReleaseTransactors) + here(NAcquireTransactors) + case NClients => site[Int]("NTILES") + 1 + case NSets => 512 + case NWays => 8 + case IsDM => here(NWays) == 1 + case OffBits => 0 + case IdxBits => log2Up(here(NSets)) + case UntagBits => here(OffBits) + here(IdxBits) + case TagBits => here(PAddrBits) - here(UntagBits) + case WayBits => log2Up(here(NWays)) + case Replacer => () => new RandomReplacement(site(NWays)) + case RowBits => site(TLDataBits) + case WordBits => 64 + case RefillCycles => site(TLDataBits)/here(RowBits) + }) + case NTiles => here[Int]("NTILES") + case NBanks => here[Int]("NBANKS") + case BankIdLSB => 5 + case BuildDRAMSideLLC => () => { + val refill = site(TLDataBits)/site(MIFDataBits) + if(site[Boolean]("USE_DRAMSIDE_LLC")) { + val tag = Mem(Bits(width = 152), 512, seqRead = true) + val data = Mem(Bits(width = 64), 4096, seqRead = true) + Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, + refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) + } else { Module(new DRAMSideLLCNull(16, refill)) } + } + case BuildCoherentMaster => (id: Int) => { + if(!site[Boolean]("USE_DRAMSIDE_LLC")) { + Module(new L2CoherenceAgent(id), here(L2HellaCacheParams)) + } else { + Module(new L2HellaCache(id), here(L2HellaCacheParams)) + } + } + //HTIF Constants + case HTIFWidth => 16 + case HTIFNSCR => 64 + case HTIFOffsetBits => here[Int]("OFFSET_BITS") + case HTIFNCores => here[Int]("NTILES") } } } +case object NTiles extends Field[Int] +case object NBanks extends Field[Int] +case object BankIdLSB extends Field[Int] +case object TileLinkL1Params extends Field[PF] +case object L2HellaCacheParams extends Field[PF] +case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike] +case object BuildCoherentMaster extends Field[Int => CoherenceAgent] +case object Coherence extends Field[CoherencePolicyWithUncached] -class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module +class OuterMemorySystem extends Module { - implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif) val io = new Bundle { - val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip + val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip val htif = (new TileLinkIO).flip - val incoherent = Vec.fill(ln.nClients){Bool()}.asInput + val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput val mem = new MemIO - val mem_backup = new MemSerializedIO(htif_width) + val mem_backup = new MemSerializedIO(params(HTIFWidth)) val mem_backup_en = Bool(INPUT) } - val refill_cycles = tl.dataBits/mif.dataBits - val (llc, masterEndpoints) = if(conf.useDRAMSideLLC) { - val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true) - val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true) - val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, - refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf)) - val mes = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i))) - (llc, mes) - } else { - val llc = Module(new DRAMSideLLCNull(16, refill_cycles)) - val mes = (0 until ln.nMasters).map(i => Module(new L2HellaCache(i))) - (llc, mes) - } + val refill_cycles = params(TLDataBits)/params(MIFDataBits) + val llc = params(BuildDRAMSideLLC)() + val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } @@ -80,8 +218,8 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) - if(ln.nMasters > 1) { - val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)) + if(params(NBanks) > 1) { + val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks))) arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache } conv.io.uncached <> arb.io.out } else { @@ -92,7 +230,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext conv.io.mem.resp <> llc.io.cpu.resp // mux between main and backup memory ports - val mem_serdes = Module(new MemSerdes(htif_width)) + val mem_serdes = Module(new MemSerdes(params(HTIFWidth))) val mem_cmdq = Module(new Queue(new MemReqCmd, 2)) mem_cmdq.io.enq <> llc.io.mem.req_cmd mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready) @@ -116,22 +254,22 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext io.mem_backup <> mem_serdes.io.narrow } -case class UncoreConfiguration(l2: L2CacheConfig, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int, useDRAMSideLLC: Boolean) -class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module +class Uncore extends Module { - implicit val (tl, mif) = (conf.tl, conf.mif) + require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits)) + val htif_width = params(HTIFWidth) val io = new Bundle { val host = new HostIO(htif_width) val mem = new MemIO - val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip - val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip - val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput + val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip + val htif = Vec.fill(params(NTiles)){new HTIFIO}.flip + val incoherent = Vec.fill(params(NTiles)){Bool()}.asInput val mem_backup = new MemSerializedIO(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits)) - val outmemsys = Module(new OuterMemorySystem(htif_width)) + val htif = Module(new HTIF(CSRs.reset)) + val outmemsys = Module(new OuterMemorySystem) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif htif.io.cpu <> io.htif @@ -140,21 +278,20 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module // Add networking headers and endpoint queues def convertAddrToBank(addr: Bits): UInt = { - require(conf.bankIdLsb + log2Up(conf.nBanks) < conf.mif.addrBits, {println("Invalid bits for bank multiplexing.")}) - addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb) + addr(params(BankIdLSB) + log2Up(params(NBanks)) - 1, params(BankIdLSB)) } (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { case ((outer, client), i) => - outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, conf.nBanks, convertAddrToBank _)) - outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, conf.nBanks, convertAddrToBank _)) + outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, params(NBanks), convertAddrToBank _)) + outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, params(NBanks), convertAddrToBank _)) outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) } // pad out the HTIF using a divided clock - val hio = Module((new SlowIO(512)) { Bits(width = htif_width+1) }) + val hio = Module((new SlowIO(512)) { Bits(width = params(HTIFWidth)+1) }) hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63 hio.io.set_divisor.bits := htif.io.scr.wdata htif.io.scr.rdata(63) := hio.io.divisor @@ -183,12 +320,12 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr } -class TopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends Bundle { - val host = new HostIO(htifWidth) +class TopIO extends Bundle { + val host = new HostIO(params(HTIFWidth)) val mem = new MemIO } -class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) { +class VLSITopIO extends TopIO { val mem_backup_en = Bool(INPUT) val in_mem_ready = Bool(OUTPUT) val in_mem_valid = Bool(INPUT) @@ -196,58 +333,27 @@ class VLSITopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends To val out_mem_valid = Bool(OUTPUT) } - class MemDessert extends Module { - implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) - val io = new MemDesserIO(params[Int]("HTIF_WIDTH")) - val x = Module(new MemDesser(params[Int]("HTIF_WIDTH"))) + val io = new MemDesserIO(params(HTIFWidth)) + val x = Module(new MemDesser(params(HTIFWidth))) io.narrow <> x.io.narrow io.wide <> x.io.wide } - class Top extends Module { - val dir = new FullRepresentation(params[Int]("NTILES")+1) - val co = if(params[Boolean]("ENABLE_SHARING")) { - if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir) - else new MSICoherence(dir) - } else { - if(params[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir) - else new MICoherence(dir) - } - implicit val ln = LogicalNetworkConfiguration(log2Up(params[Int]("NTILES"))+1, params[Int]("NBANKS"), params[Int]("NTILES")+1) - implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS")) - implicit val tl = TileLinkConfiguration(co = co, ln = ln, - addrBits = as.paddrBits-params[Int]("OFFSET_BITS"), - clientXactIdBits = log2Up(params[Int]("NL2_REL_XACTS")+params[Int]("NL2_ACQ_XACTS")), - masterXactIdBits = 2*log2Up(params[Int]("NMSHRS")*params[Int]("NTILES")+1), - dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8, - writeMaskBits = params[Int]("WRITE_MASK_BITS"), - wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"), - atomicOpBits = params[Int]("ATOMIC_OP_BITS")) - implicit val l2 = L2CacheConfig(512, 8, 1, 1, params[Int]("NL2_REL_XACTS"), params[Int]("NL2_ACQ_XACTS"), tl, as) - implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) - implicit val uc = UncoreConfiguration(l2, tl, mif, params[Int]("NTILES"), params[Int]("NBANKS"), bankIdLsb = 5, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"), useDRAMSideLLC = params[Boolean]("USE_DRAMSIDE_LLC")) + //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) + //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 64, 2)) - val dc = DCacheConfig(sets = 128, ways = 4, - tl = tl, as = as, - ntlb = 8, nmshr = params[Int]("NMSHRS"), nrpq = 16, nsdq = 17, - reqtagbits = -1, databits = -1) - val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) - val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val rc = RocketConfiguration(tl, as, ic, dc - // rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c)) - ) + val nTiles = params(NTiles) + val io = new VLSITopIO - val io = new VLSITopIO(params[Int]("HTIF_WIDTH")) + params.alter(params(TileLinkL1Params)) + val resetSigs = Vec.fill(nTiles){Bool()} + val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) + val uncore = Module(new Uncore) - val resetSigs = Vec.fill(uc.nTiles){Bool()} - val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) - val uncore = Module(new Uncore(params[Int]("HTIF_WIDTH"))) - - for (i <- 0 until uc.nTiles) { + for (i <- 0 until nTiles) { val hl = uncore.io.htif(i) val tl = uncore.io.tiles(i) val il = uncore.io.incoherent(i) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index c2e24565..b3166cd1 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -6,17 +6,15 @@ import rocket._ import DRAMModel._ import DRAMModel.MemModelConstants._ -class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) - extends Module { - implicit val (tl, ln, l2, mif) = (conf.tl, conf.tl.ln, conf.l2, conf.mif) +class FPGAOuterMemorySystem extends Module { val io = new Bundle { - val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip + val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip val htif = (new TileLinkIO).flip - val incoherent = Vec.fill(ln.nClients){Bool()}.asInput + val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput val mem = new MemIO } - val master = Module(new L2CoherenceAgent(0)) + val master = Module(new L2CoherenceAgent(0), params(L2HellaCacheParams)) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters.head <> master.io.inner @@ -25,24 +23,21 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfigurat val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) conv.io.uncached <> master.io.outer io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2) - io.mem.req_data <> Queue(conv.io.mem.req_data, tl.dataBits/mif.dataBits) + io.mem.req_data <> Queue(conv.io.mem.req_data, params(TLDataBits)/params(MIFDataBits)) conv.io.mem.resp <> Queue(io.mem.resp) } -case class FPGAUncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nSCR: Int, offsetBits: Int) - -class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) - extends Module { - implicit val (tl, ln, mif) = (conf.tl, conf.tl.ln, conf.mif) +class FPGAUncore extends Module { + val (htifw, nTiles) = (params(HTIFWidth),params(NTiles)) val io = new Bundle { - val host = new HostIO(htif_width) + val host = new HostIO(htifw) val mem = new MemIO - val tiles = Vec.fill(conf.nTiles){new TileLinkIO}.flip - val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip - val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput + val tiles = Vec.fill(nTiles){new TileLinkIO}.flip + val htif = Vec.fill(nTiles){new HTIFIO}.flip + val incoherent = Vec.fill(nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits)) - val outmemsys = Module(new FPGAOuterMemorySystem(htif_width)) + val htif = Module(new HTIF(CSRs.reset)) + val outmemsys = Module(new FPGAOuterMemorySystem) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif htif.io.cpu <> io.htif @@ -62,13 +57,13 @@ class FPGAUncore(htif_width: Int)(implicit conf: FPGAUncoreConfiguration) htif.io.host.in <> io.host.in } -class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf) +class FPGATopIO extends TopIO class FPGATop extends Module { + /* val ntiles = 1 val nmshrs = 2 val htif_width = 16 - val co = new MESICoherence(new FullRepresentation(ntiles+1)) implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS")) @@ -88,14 +83,18 @@ class FPGATop extends Module { val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1) val rc = RocketConfiguration(tl, as, ic, dc, fastMulDiv = false) +*/ - val io = new FPGATopIO(htif_width) + val nTiles = params(NTiles) + val io = new FPGATopIO - val resetSigs = Vec.fill(uc.nTiles){Bool()} - val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc))) - val uncore = Module(new FPGAUncore(htif_width)) + params.alter(params(TileLinkL1Params)) - for (i <- 0 until uc.nTiles) { + val resetSigs = Vec.fill(nTiles){Bool()} + val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) + val uncore = Module(new FPGAUncore) + + for (i <- 0 until nTiles) { val hl = uncore.io.htif(i) val tl = uncore.io.tiles(i) val il = uncore.io.incoherent(i) diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala index 5deda918..3a949d9e 100644 --- a/src/main/scala/network.scala +++ b/src/main/scala/network.scala @@ -6,7 +6,7 @@ import scala.reflect._ import scala.reflect.runtime.universe._ object TileLinkHeaderOverwriter { - def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = { + def apply[T <: ClientSourcedMessage](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = { val out = in.clone.asDirectionless out.bits.payload := in.bits.payload out.bits.header.src := UInt(clientId) @@ -15,29 +15,26 @@ object TileLinkHeaderOverwriter { in.ready := out.ready out } - def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt)(implicit conf: TileLinkConfiguration): DecoupledIO[LogicalNetworkIO[T]] = { + def apply[T <: ClientSourcedMessage with HasPhysicalAddress](in: DecoupledIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = { val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false) out.bits.header.dst := (if(nBanks > 1) addrConvert(in.bits.payload.addr) else UInt(0)) out } } -class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) - extends LogicalNetwork[TileLinkIO]()(conf.ln) { - implicit val (ln, co) = (conf.ln, conf.co) +class ReferenceChipCrossbarNetwork extends LogicalNetwork { val io = new Bundle { - val clients = Vec.fill(ln.nClients){(new TileLinkIO).flip} - val masters = Vec.fill(ln.nMasters){new TileLinkIO} + val clients = Vec.fill(params(LNClients)){(new TileLinkIO).flip} + val masters = Vec.fill(params(LNMasters)){new TileLinkIO} } - implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks - + val n = params(LNEndpoints) // Actually instantiate the particular networks required for TileLink - val acqNet = Module(new BasicCrossbar(new Acquire)) - val relNet = Module(new BasicCrossbar(new Release)) - val prbNet = Module(new BasicCrossbar(new Probe)) - val gntNet = Module(new BasicCrossbar(new Grant)) - val ackNet = Module(new BasicCrossbar(new Finish)) + val acqNet = Module(new BasicCrossbar(n, new Acquire)) + val relNet = Module(new BasicCrossbar(n, new Release)) + val prbNet = Module(new BasicCrossbar(n, new Probe)) + val gntNet = Module(new BasicCrossbar(n, new Grant)) + val ackNet = Module(new BasicCrossbar(n, new Finish)) // Aliases for the various network IO bundle types type FBCIO[T <: Data] = DecoupledIO[PhysicalNetworkIO[T]] @@ -57,16 +54,16 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) } def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = { val out = DefaultFromCrossbarShim(in) - out.bits.header.src := in.bits.header.src - UInt(ln.nMasters) + out.bits.header.src := in.bits.header.src - UInt(params(LNMasters)) out } def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = { val out = DefaultFromCrossbarShim(in) - out.bits.header.dst := in.bits.header.dst - UInt(ln.nMasters) + out.bits.header.dst := in.bits.header.dst - UInt(params(LNMasters)) out } def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = { - val out = Decoupled(new PhysicalNetworkIO(in.bits.payload)).asDirectionless + val out = Decoupled(new PhysicalNetworkIO(n,in.bits.payload)).asDirectionless out.bits.header := in.bits.header out.bits.payload := in.bits.payload out.valid := in.valid @@ -75,12 +72,12 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) } def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = { val out = DefaultToCrossbarShim(in) - out.bits.header.dst := in.bits.header.dst + UInt(ln.nMasters) + out.bits.header.dst := in.bits.header.dst + UInt(params(LNMasters)) out } def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = { val out = DefaultToCrossbarShim(in) - out.bits.header.src := in.bits.header.src + UInt(ln.nMasters) + out.bits.header.src := in.bits.header.src + UInt(params(LNMasters)) out } @@ -112,11 +109,11 @@ class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) typeTag[T].tpe match{ case t if t <:< typeTag[ClientSourcedMessage].tpe => { io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id), physIO.out(id), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) } - io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) } + io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), ClientToCrossbarShim, CrossbarToMasterShim) } } case t if t <:< typeTag[MasterSourcedMessage].tpe => { io.masters.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](true, physIO.in(id), physIO.out(id), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) } - io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+ln.nMasters), physIO.out(id+ln.nMasters), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) } + io.clients.zipWithIndex.map{ case (i, id) => doFIFOHookup[T](false, physIO.in(id+params(LNMasters)), physIO.out(id+params(LNMasters)), getLogIO(i), MasterToCrossbarShim, CrossbarToClientShim) } } case _ => require(false, "Unknown message sourcing.") } diff --git a/uncore b/uncore index ebe0f493..e2f36060 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit ebe0f493a62641a71caec9f2959a4f57e2c16b4e +Subproject commit e2f3606041d97eedb10964e48e57b4b093ab73c6 From 1983260e6f4cd8a30fb8535b873090ce23fd49e0 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 10 Aug 2014 23:08:21 -0700 Subject: [PATCH 05/16] a few more fixes. some param lookups fail (here() in Alter blocks) --- rocket | 2 +- src/main/scala/RocketChip.scala | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/rocket b/rocket index 6beea1de..f0f84ed6 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 6beea1debbdd8115f45d02318210df624e67e9f8 +Subproject commit f0f84ed6f953388a046c3296ccd0a3640ca6bd48 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 5bfa8698..d14436e1 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -109,10 +109,10 @@ class DefaultConfig extends ChiselConfig { case Entries => 62 case NRAS => 2 case MatchBits => site(PgIdxBits) - case Pages => ((1 max(log2Up(here(Entries))))+1)/2*2 + case Pages => ((1 max(log2Up(site(Entries))))+1)/2*2 //TODO PARAMS no here? // control logic assumes 2 divides pages case OpaqueBits => log2Up(here(Entries)) - case NBHT => 1 << log2Up(here(Entries)*2) + case NBHT => 1 << log2Up(site(Entries)*2) //TODO PARAMS no here? }) //MemoryConstants case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 @@ -132,9 +132,9 @@ class DefaultConfig extends ChiselConfig { case TileLinkL1Params => Alter({ case LNMasters => site[Int]("NBANKS") case LNClients => site[Int]("NTILES")+1 - case LNEndpoints => here(LNMasters) + here(LNClients) + case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients) case TLCoherence => site(Coherence) - case TLAddrBits => site[Int]("PADDR_BITS") - site[Int]("OFFSET_BITS") + case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS") case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS")) case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1) case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8 @@ -348,9 +348,10 @@ class Top extends Module { val nTiles = params(NTiles) val io = new VLSITopIO - params.alter(params(TileLinkL1Params)) + val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below? + params.alter(tl) val resetSigs = Vec.fill(nTiles){Bool()} - val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) + val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient? val uncore = Module(new Uncore) for (i <- 0 until nTiles) { From 7f07771600bc08d5856280f4b14044a0e24d786b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 11 Aug 2014 18:37:10 -0700 Subject: [PATCH 06/16] Cache utility traits. Completely compiles, asm tests hang. --- rocket | 2 +- src/main/scala/RocketChip.scala | 82 +++++++++------------------------ uncore | 2 +- 3 files changed, 25 insertions(+), 61 deletions(-) diff --git a/rocket b/rocket index f0f84ed6..44618ac0 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit f0f84ed6f953388a046c3296ccd0a3640ca6bd48 +Subproject commit 44618ac072f01001e56d168c858885da106b70b0 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d14436e1..c78358f7 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -60,59 +60,30 @@ class DefaultConfig extends ChiselConfig { case NTLBEntries => 8 case CoreReqTagBits => site(DcacheReqTagBits) case CoreDataBits => site(XprLen) - case RowWords => 2 case ECCCode => new IdentityCode + case LRSCCycles => 32 //From uncore/cache.scala case NSets => 128 case NWays => 4 - case IsDM => here(NWays) == 1 - case OffBits => log2Up(site(TLDataBits)) - case IdxBits => log2Up(here(NSets)) - case UntagBits => here(OffBits) + here(IdxBits) - case TagBits => here(PAddrBits) - here(UntagBits) - case WayBits => log2Up(here(NWays)) - case Replacer => () => new RandomReplacement(site(NWays)) - case RowBits => here(RowWords)*here(CoreDataBits) - case WordBits => here(CoreDataBits) - case RefillCycles => site(TLDataBits)/here(RowBits) - //Derived - case MaxAddrBits => math.max(site(PPNBits),site(VPNBits)+1) + site(PgIdxBits) - case CoreDataBytes => here(CoreDataBits)/8 - case WordOffBits => log2Up(here(CoreDataBytes)) - case RowBytes => here(RowWords)*here(CoreDataBytes) - case RowOffBits => log2Up(here(RowBytes)) - case DoNarrowRead => here(CoreDataBits)*here(NWays) % here(RowBits) == 0 - case EncDataBits => here(ECCCode).width(here(CoreDataBits)) - case EncRowBits => here(RowWords)*here(EncDataBits) - case LRSCCycles => 32 + case BlockOffBits => log2Up(site(TLDataBits)/8) + case RowBits => 2*site(XprLen) + case WordBits => site(XprLen) //here(CoreDataBits) TODO + case Replacer => () => new RandomReplacement(4)//site(NWays)) TODO }) case RocketFrontendParams => Alter({ case InstBytes => 4 - case RowBytes => 16 case NTLBEntries => 8 case ECCCode => new IdentityCode + //From rocket/btb.scala + case BTBEntries => 62 + case NRAS => 2 //From uncore/cache.scala case NSets => 128 case NWays => 2 - case IsDM => here(NWays) == 1 - case OffBits => log2Up(site(TLDataBits)/8) - case IdxBits => log2Up(here(NSets)) - case UntagBits => here(OffBits) + here(IdxBits) - case TagBits => here(PAddrBits) - here(UntagBits) - case WayBits => log2Up(here(NWays)) - case Replacer => () => new RandomReplacement(site(NWays)) - case RowBits => here(RowBytes)*8 - case RefillCycles => site(TLDataBits)/here(RowBits) - case RowOffBits => log2Up(here(RowBytes)) - }) - case CoreBTBParams => Alter({ - case Entries => 62 - case NRAS => 2 - case MatchBits => site(PgIdxBits) - case Pages => ((1 max(log2Up(site(Entries))))+1)/2*2 //TODO PARAMS no here? - // control logic assumes 2 divides pages - case OpaqueBits => log2Up(here(Entries)) - case NBHT => 1 << log2Up(site(Entries)*2) //TODO PARAMS no here? + case BlockOffBits => log2Up(site(TLDataBits)/8) + case RowBits => 16*8 + case WordBits => site(XprLen) //TODO merge with instbytes? + case Replacer => () => new RandomReplacement(2)//site(NWays)) TODO }) //MemoryConstants case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 @@ -145,20 +116,13 @@ class DefaultConfig extends ChiselConfig { case L2HellaCacheParams => Alter({ case NReleaseTransactors => site[Int]("NL2_REL_XACTS") case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS") - case NTransactors => here(NReleaseTransactors) + here(NAcquireTransactors) case NClients => site[Int]("NTILES") + 1 case NSets => 512 case NWays => 8 - case IsDM => here(NWays) == 1 - case OffBits => 0 - case IdxBits => log2Up(here(NSets)) - case UntagBits => here(OffBits) + here(IdxBits) - case TagBits => here(PAddrBits) - here(UntagBits) - case WayBits => log2Up(here(NWays)) - case Replacer => () => new RandomReplacement(site(NWays)) + case BlockOffBits => 0 case RowBits => site(TLDataBits) - case WordBits => 64 - case RefillCycles => site(TLDataBits)/here(RowBits) + case WordBits => site(XprLen) + case Replacer => () => new RandomReplacement(8)//site(NWays)) }) case NTiles => here[Int]("NTILES") case NBanks => here[Int]("NBANKS") @@ -172,11 +136,11 @@ class DefaultConfig extends ChiselConfig { refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) } else { Module(new DRAMSideLLCNull(16, refill)) } } - case BuildCoherentMaster => (id: Int) => { + case BuildCoherentMaster => (id: Int, p: Some[Parameters]) => { if(!site[Boolean]("USE_DRAMSIDE_LLC")) { - Module(new L2CoherenceAgent(id), here(L2HellaCacheParams)) + Module(new L2CoherenceAgent(id))(p) } else { - Module(new L2HellaCache(id), here(L2HellaCacheParams)) + Module(new L2HellaCache(id))(p) } } //HTIF Constants @@ -194,7 +158,7 @@ case object BankIdLSB extends Field[Int] case object TileLinkL1Params extends Field[PF] case object L2HellaCacheParams extends Field[PF] case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike] -case object BuildCoherentMaster extends Field[Int => CoherenceAgent] +case object BuildCoherentMaster extends Field[(Int,Option[Parameters]) => CoherenceAgent] case object Coherence extends Field[CoherencePolicyWithUncached] class OuterMemorySystem extends Module @@ -210,9 +174,10 @@ class OuterMemorySystem extends Module val refill_cycles = params(TLDataBits)/params(MIFDataBits) val llc = params(BuildDRAMSideLLC)() - val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)) + val l2p = Some(params.alter(params(L2HellaCacheParams))) + val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)(_,l2p)) - val net = Module(new ReferenceChipCrossbarNetwork) + val net = Module(new ReferenceChipCrossbarNetwork)(l2p) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } @@ -349,10 +314,9 @@ class Top extends Module { val io = new VLSITopIO val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below? - params.alter(tl) val resetSigs = Vec.fill(nTiles){Bool()} val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient? - val uncore = Module(new Uncore) + val uncore = Module(new Uncore, tl) for (i <- 0 until nTiles) { val hl = uncore.io.htif(i) diff --git a/uncore b/uncore index e2f36060..041a1ec1 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit e2f3606041d97eedb10964e48e57b4b093ab73c6 +Subproject commit 041a1ec127634413314bc9d6241fd12860950e70 From 0ca24a5d9176b732bb9ad7b381b2701b2262185a Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 12 Aug 2014 10:35:39 -0700 Subject: [PATCH 07/16] fix debug flags --- emulator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/emulator/Makefile b/emulator/Makefile index 4f27f61e..e117f026 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -17,7 +17,7 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) -CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src --configInstance $(PROJECT).$(CONFIG) +CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --configInstance $(PROJECT).$(CONFIG) --targetDir emulator/generated-src CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala From 74796868e7fbfafd8266b58609f05938473a1712 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 12 Aug 2014 10:58:09 -0700 Subject: [PATCH 08/16] chisel bump --- chisel | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel b/chisel index e600be36..7b6a33ef 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit e600be365d8fc5a9a868ed40ad72489817e79b44 +Subproject commit 7b6a33ef7ae015a15c54b0bdc5113b01a098a2b3 From 910c8868373b864aa3de3c824003f59efd843844 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 12 Aug 2014 14:53:19 -0700 Subject: [PATCH 09/16] bump chisel --- chisel | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel b/chisel index 7b6a33ef..4728ab65 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 7b6a33ef7ae015a15c54b0bdc5113b01a098a2b3 +Subproject commit 4728ab65aca8a47b3889d7fe5006553cda9a0a4c From 1563c1bb36eeba69fb3ae10e03aff3f2da1cbef3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 12 Aug 2014 15:00:54 -0700 Subject: [PATCH 10/16] Fixed cache params. Asm and bmark tests pass. --- src/main/scala/RocketChip.scala | 2 +- uncore | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index c78358f7..2ae088ab 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -310,7 +310,7 @@ class Top extends Module { //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val nTiles = params(NTiles) + val nTiles = params[Int]("NTILES") val io = new VLSITopIO val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below? diff --git a/uncore b/uncore index 041a1ec1..37fdf255 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 041a1ec127634413314bc9d6241fd12860950e70 +Subproject commit 37fdf25582b9c0ef48dceecb76416c955f0bc81e From 2741bbf2b9013e98ab2bf6e5f3377f4df9b0fdae Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 19 Aug 2014 13:53:24 -0700 Subject: [PATCH 11/16] Point rocket/ to rocket-staging repo --- .gitmodules | 2 +- rocket | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 58554827..a88351c9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -9,7 +9,7 @@ url = git@github.com:ucb-bar/riscv-tools.git [submodule "rocket"] path = rocket - url = git@github.com:ucb-bar/riscv-rocket.git + url = git@github.com:ucb-bar/rocket-staging.git [submodule "chisel"] path = chisel url = git@github.com:ucb-bar/chisel.git diff --git a/rocket b/rocket index 44618ac0..50c5310b 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 44618ac072f01001e56d168c858885da106b70b0 +Subproject commit 50c5310b56d589a0e626d4c68cb8cd73a698727e From a41d55b643f380a0ac482b59759953009bca8fa9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sat, 23 Aug 2014 01:26:03 -0700 Subject: [PATCH 12/16] Final parameter refactor. --- chisel | 2 +- rocket | 2 +- src/main/scala/PublicConfigs.scala | 145 +++++++++++++++++++++++++ src/main/scala/RocketChip.scala | 165 ++--------------------------- src/main/scala/fpga.scala | 4 +- uncore | 2 +- 6 files changed, 157 insertions(+), 163 deletions(-) create mode 100644 src/main/scala/PublicConfigs.scala diff --git a/chisel b/chisel index 4728ab65..00d24693 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 4728ab65aca8a47b3889d7fe5006553cda9a0a4c +Subproject commit 00d24693d4b656508fc50b48f411057d06c38f4d diff --git a/rocket b/rocket index 50c5310b..54fe89fe 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 50c5310b56d589a0e626d4c68cb8cd73a698727e +Subproject commit 54fe89fe3bdc9e9cd2caf7adab68bb6bb81b2b9c diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala new file mode 100644 index 00000000..7769576c --- /dev/null +++ b/src/main/scala/PublicConfigs.scala @@ -0,0 +1,145 @@ +package referencechip + +import Chisel._ +import uncore._ +import rocket._ +import rocket.Util._ + +class DefaultVLSIConfig extends DefaultConfig +class DefaultFPGAConfig extends DefaultConfig +class DefaultCPPConfig extends DefaultConfig +class DefaultConfig extends ChiselConfig { + val top:World.TopDefs = { + (pname,site,here) => pname match { + //Params used by all caches + case ECCCode => None + case WordBits => site(XprLen) + case Replacer => () => new RandomReplacement(site(NWays)) + case BlockOffBits => site(CacheName) match { + case "L1I" | "L1D" => log2Up(site(TLDataBits)/8) + case "L2" => 0 + } + case NSets => site(CacheName) match { + case "L1I" => 128 + case "L1D" => 128 + case "L2" => 512 + } + case NWays => site(CacheName) match { + case "L1I" => 2 + case "L1D" => 4 + case "L2" => 8 + } + case RowBits => site(CacheName) match { + case "L1I" => 4*site(CoreInstBits) + case "L1D" => 2*site(CoreDataBits) + case "L2" => site(TLDataBits) + } + //L1InstCache + case NITLBEntries => 8 + case NBTBEntries => 62 + case NRAS => 2 + //L1DataCache + case NDTLBEntries => 8 + case StoreDataQueueDepth => 17 + case ReplayQueueDepth => 16 + case NMSHRs => site[Int]("NMSHRS") + case LRSCCycles => 32 + //L2CacheParams + case NReleaseTransactors => site[Int]("NL2_REL_XACTS") + case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS") + case NClients => site(NTiles) + 1 + //Tile Constants + case BuildRoCC => None + case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) + case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) + case NPTWPorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 3) + //Rocket Core Constants + case RetireWidth => 1 + case UseVM => true + case FastLoadWord => true + case FastLoadByte => false + case FastMulDiv => true + case XprLen => 64 + case NMultXpr => 32 + case BuildFPU => Some(() => new FPU) + case SFMALatency => 2 + case DFMALatency => 3 + case CoreInstBits => 32 + case CoreDataBits => site(XprLen) + case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts)) + //HTIF Parameters + case HTIFWidth => 16 + case HTIFNSCR => 64 + case HTIFOffsetBits => site(CacheBlockOffsetBits) + case HTIFNCores => site(NTiles) + //Memory Parameters + case PAddrBits => 32 + case VAddrBits => 43 + case PgIdxBits => 13 + case ASIdBits => 7 + case PermBits => 6 + case PPNBits => site(PAddrBits) - site(PgIdxBits) + case VPNBits => site(VAddrBits) - site(PgIdxBits) + case MIFTagBits => 5 + case MIFDataBits => 128 + case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) + case MIFDataBeats => 4 + //Uncore Paramters + case LNMasters => site(NBanks) + case LNClients => site(NTiles)+1 + case LNEndpoints => site(LNMasters) + site(LNClients) + case TLCoherence => site(Coherence) + case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) + case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors)) + case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts)) + case TLDataBits => site(CacheBlockBytes)*8 + case TLWriteMaskBits => 6 + case TLWordAddrBits => 3 + case TLAtomicOpBits => 4 + case NTiles => here[Int]("NTILES") + case NBanks => here[Int]("NBANKS") + case BankIdLSB => 5 + case CacheBlockBytes => 64 + case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) + case BuildDRAMSideLLC => () => { + val refill = site(TLDataBits)/site(MIFDataBits) + if(site[Boolean]("USE_DRAMSIDE_LLC")) { + val tag = Mem(Bits(width = 152), 512, seqRead = true) + val data = Mem(Bits(width = 64), 4096, seqRead = true) + Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, + refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) + } else { Module(new DRAMSideLLCNull(16, refill)) } + } + case BuildCoherentMaster => (id: Int) => { + if(!site[Boolean]("USE_DRAMSIDE_LLC")) { + Module(new L2CoherenceAgent(id), { case CacheName => "L2" }) + } else { + Module(new L2HellaCache(id), { case CacheName => "L2" }) + } + } + case Coherence => { + val dir = new FullRepresentation(site(NClients)) + val enSharing = site[Boolean]("ENABLE_SHARING") + val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE") + if(enSharing) { + if(enCleanEx) new MESICoherence(dir) + else new MSICoherence(dir) + } else { + if(enCleanEx) new MEICoherence(dir) + else new MICoherence(dir) + } + } + //DesignSpaceConstants //TODO KNOBS + case "NTILES" => 1 + case "NBANKS" => 1 + case "HTIF_WIDTH" => 16 + case "ENABLE_SHARING" => true + case "ENABLE_CLEAN_EXCLUSIVE" => true + case "USE_DRAMSIDE_LLC" => true + case "NL2_REL_XACTS" => 1 + case "NL2_ACQ_XACTS" => 7 + case "NMSHRS" => 2 + } + } +} + diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 2ae088ab..505ee52d 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -5,160 +5,13 @@ import uncore._ import rocket._ import rocket.Util._ -class DefaultVLSIConfig extends DefaultConfig -class DefaultFPGAConfig extends DefaultConfig -class DefaultCPPConfig extends DefaultConfig -class DefaultConfig extends ChiselConfig { - val top:World.TopDefs = { - (pname,site,here) => pname match { - //DesignSpaceConstants - case "NTILES" => 1 - case "NBANKS" => 1 - case "HTIF_WIDTH" => 16 - case "ENABLE_SHARING" => true - case "ENABLE_CLEAN_EXCLUSIVE" => true - case "USE_DRAMSIDE_LLC" => true - case "NL2_REL_XACTS" => 1 - case "NL2_ACQ_XACTS" => 7 - case "NMSHRS" => 2 - //Coherence - case Coherence => { - val dir = new FullRepresentation(site[Int]("NTILES")+1) - if(site[Boolean]("ENABLE_SHARING")) { - if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MESICoherence(dir) - else new MSICoherence(dir) - } else { - if(site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")) new MEICoherence(dir) - else new MICoherence(dir) - } - } - //Rocket Constants - // Number of ports into D$: 1 from core, 1 from PTW, maybe 1 from RoCC - case NDCachePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) - // Number of ports to outer memory system from tile: 1 from I$, 1 from D$, maybe 1 from Rocc - case NTilePorts => 2 + (if(site(BuildRoCC).isEmpty) 0 else 1) - case BuildRoCC => None - case RetireWidth => 1 - case UseVM => true - case FastLoadWord => true - case FastLoadByte => false - case FastMulDiv => true - case DcacheReqTagBits => 7 + log2Up(here(NDCachePorts)) - case XprLen => 64 - case NXpr => 32 - case NXprBits => log2Up(here(NXpr)) - case BuildFPU => Some(() => new FPU) - case FPUParams => Alter({ - case SFMALatency => 2 - case DFMALatency => 3 - }) - case RocketDCacheParams => Alter({ - //L1 Specific - case StoreDataQueueDepth => 17 - case ReplayQueueDepth => 16 - case NMSHRs => site[Int]("NMSHRS") - case NTLBEntries => 8 - case CoreReqTagBits => site(DcacheReqTagBits) - case CoreDataBits => site(XprLen) - case ECCCode => new IdentityCode - case LRSCCycles => 32 - //From uncore/cache.scala - case NSets => 128 - case NWays => 4 - case BlockOffBits => log2Up(site(TLDataBits)/8) - case RowBits => 2*site(XprLen) - case WordBits => site(XprLen) //here(CoreDataBits) TODO - case Replacer => () => new RandomReplacement(4)//site(NWays)) TODO - }) - case RocketFrontendParams => Alter({ - case InstBytes => 4 - case NTLBEntries => 8 - case ECCCode => new IdentityCode - //From rocket/btb.scala - case BTBEntries => 62 - case NRAS => 2 - //From uncore/cache.scala - case NSets => 128 - case NWays => 2 - case BlockOffBits => log2Up(site(TLDataBits)/8) - case RowBits => 16*8 - case WordBits => site(XprLen) //TODO merge with instbytes? - case Replacer => () => new RandomReplacement(2)//site(NWays)) TODO - }) - //MemoryConstants - case "CACHE_DATA_SIZE_IN_BYTES" => 1 << 6 - case "OFFSET_BITS" => log2Up(here[Int]("CACHE_DATA_SIZE_IN_BYTES")) - case PAddrBits => 32 - case VAddrBits => 43 - case PgIdxBits => 13 - case ASIdBits => 7 - case PermBits => 6 - case PPNBits => here(PAddrBits) - here(PgIdxBits) - case VPNBits => here(VAddrBits) - here(PgIdxBits) - case MIFTagBits => 5 - case MIFDataBits => 128 - case MIFAddrBits => here(PAddrBits) - here[Int]("OFFSET_BITS") - case MIFDataBeats => 4 - //Uncore Constants - case TileLinkL1Params => Alter({ - case LNMasters => site[Int]("NBANKS") - case LNClients => site[Int]("NTILES")+1 - case LNEndpoints => site[Int]("NBANKS") + site[Int]("NTILES")+1 // TODO PARAMS why broken?: site(LNMasters) +site(LNClients) - case TLCoherence => site(Coherence) - case TLAddrBits => site(PAddrBits) - site[Int]("OFFSET_BITS") - case TLMasterXactIdBits => log2Up(site[Int]("NL2_REL_XACTS")+site[Int]("NL2_ACQ_XACTS")) - case TLClientXactIdBits => 2*log2Up(site[Int]("NMSHRS")*site[Int]("NTILES")+1) - case TLDataBits => site[Int]("CACHE_DATA_SIZE_IN_BYTES")*8 - case TLWriteMaskBits => 6 - case TLWordAddrBits => 3 - case TLAtomicOpBits => 4 - }) - case L2HellaCacheParams => Alter({ - case NReleaseTransactors => site[Int]("NL2_REL_XACTS") - case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS") - case NClients => site[Int]("NTILES") + 1 - case NSets => 512 - case NWays => 8 - case BlockOffBits => 0 - case RowBits => site(TLDataBits) - case WordBits => site(XprLen) - case Replacer => () => new RandomReplacement(8)//site(NWays)) - }) - case NTiles => here[Int]("NTILES") - case NBanks => here[Int]("NBANKS") - case BankIdLSB => 5 - case BuildDRAMSideLLC => () => { - val refill = site(TLDataBits)/site(MIFDataBits) - if(site[Boolean]("USE_DRAMSIDE_LLC")) { - val tag = Mem(Bits(width = 152), 512, seqRead = true) - val data = Mem(Bits(width = 64), 4096, seqRead = true) - Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, - refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) - } else { Module(new DRAMSideLLCNull(16, refill)) } - } - case BuildCoherentMaster => (id: Int, p: Some[Parameters]) => { - if(!site[Boolean]("USE_DRAMSIDE_LLC")) { - Module(new L2CoherenceAgent(id))(p) - } else { - Module(new L2HellaCache(id))(p) - } - } - //HTIF Constants - case HTIFWidth => 16 - case HTIFNSCR => 64 - case HTIFOffsetBits => here[Int]("OFFSET_BITS") - case HTIFNCores => here[Int]("NTILES") - } - } -} - case object NTiles extends Field[Int] case object NBanks extends Field[Int] case object BankIdLSB extends Field[Int] -case object TileLinkL1Params extends Field[PF] -case object L2HellaCacheParams extends Field[PF] +case object CacheBlockBytes extends Field[Int] +case object CacheBlockOffsetBits extends Field[Int] case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike] -case object BuildCoherentMaster extends Field[(Int,Option[Parameters]) => CoherenceAgent] +case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent] case object Coherence extends Field[CoherencePolicyWithUncached] class OuterMemorySystem extends Module @@ -174,10 +27,9 @@ class OuterMemorySystem extends Module val refill_cycles = params(TLDataBits)/params(MIFDataBits) val llc = params(BuildDRAMSideLLC)() - val l2p = Some(params.alter(params(L2HellaCacheParams))) - val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)(_,l2p)) + val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)) - val net = Module(new ReferenceChipCrossbarNetwork)(l2p) + val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } @@ -310,13 +162,12 @@ class Top extends Module { //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - val nTiles = params[Int]("NTILES") + val nTiles = params(NTiles) val io = new VLSITopIO - val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below? val resetSigs = Vec.fill(nTiles){Bool()} - val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)), tl))//TODO PARAMS above alter() is insufficient? - val uncore = Module(new Uncore, tl) + val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) + val uncore = Module(new Uncore) for (i <- 0 until nTiles) { val hl = uncore.io.htif(i) diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index b3166cd1..50184a0b 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -14,7 +14,7 @@ class FPGAOuterMemorySystem extends Module { val mem = new MemIO } - val master = Module(new L2CoherenceAgent(0), params(L2HellaCacheParams)) + val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"}) val net = Module(new ReferenceChipCrossbarNetwork) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters.head <> master.io.inner @@ -88,8 +88,6 @@ class FPGATop extends Module { val nTiles = params(NTiles) val io = new FPGATopIO - params.alter(params(TileLinkL1Params)) - val resetSigs = Vec.fill(nTiles){Bool()} val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) val uncore = Module(new FPGAUncore) diff --git a/uncore b/uncore index 37fdf255..44f51125 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 37fdf25582b9c0ef48dceecb76416c955f0bc81e +Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5 From bf356b9cb4a13c8261dde638a74695ad62d5621b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 24 Aug 2014 19:30:53 -0700 Subject: [PATCH 13/16] Refactor to combine fpga and vlsi tops, part 1 --- src/main/scala/PublicConfigs.scala | 77 ++++++------ src/main/scala/RocketChip.scala | 194 ++++++++++++----------------- src/main/scala/fpga.scala | 103 +-------------- src/main/scala/vlsi.scala | 66 ++++++++++ uncore | 2 +- 5 files changed, 186 insertions(+), 256 deletions(-) create mode 100644 src/main/scala/vlsi.scala diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala index 7769576c..8fd57a18 100644 --- a/src/main/scala/PublicConfigs.scala +++ b/src/main/scala/PublicConfigs.scala @@ -11,6 +11,23 @@ class DefaultCPPConfig extends DefaultConfig class DefaultConfig extends ChiselConfig { val top:World.TopDefs = { (pname,site,here) => pname match { + //HTIF Parameters + case HTIFWidth => 16 + case HTIFNSCR => 64 + case HTIFOffsetBits => site(CacheBlockOffsetBits) + case HTIFNCores => site(NTiles) + //Memory Parameters + case PAddrBits => 32 + case VAddrBits => 43 + case PgIdxBits => 13 + case ASIdBits => 7 + case PermBits => 6 + case PPNBits => site(PAddrBits) - site(PgIdxBits) + case VPNBits => site(VAddrBits) - site(PgIdxBits) + case MIFTagBits => 5 + case MIFDataBits => 128 + case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) + case MIFDataBeats => site(TLDataBits)/site(MIFDataBits) //Params used by all caches case ECCCode => None case WordBits => site(XprLen) @@ -21,12 +38,12 @@ class DefaultConfig extends ChiselConfig { } case NSets => site(CacheName) match { case "L1I" => 128 - case "L1D" => 128 + case "L1D" => Knob("L1D_SETS") //128 case "L2" => 512 } case NWays => site(CacheName) match { case "L1I" => 2 - case "L1D" => 4 + case "L1D" => Knob("L1D_WAYS") //4 case "L2" => 8 } case RowBits => site(CacheName) match { @@ -42,11 +59,11 @@ class DefaultConfig extends ChiselConfig { case NDTLBEntries => 8 case StoreDataQueueDepth => 17 case ReplayQueueDepth => 16 - case NMSHRs => site[Int]("NMSHRS") + case NMSHRs => Knob("L1D_MSHRS") case LRSCCycles => 32 //L2CacheParams - case NReleaseTransactors => site[Int]("NL2_REL_XACTS") - case NAcquireTransactors => site[Int]("NL2_ACQ_XACTS") + case NReleaseTransactors => Knob("L2_REL_XACTS") + case NAcquireTransactors => Knob("L2_ACQ_XACTS") case NClients => site(NTiles) + 1 //Tile Constants case BuildRoCC => None @@ -67,23 +84,6 @@ class DefaultConfig extends ChiselConfig { case CoreInstBits => 32 case CoreDataBits => site(XprLen) case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts)) - //HTIF Parameters - case HTIFWidth => 16 - case HTIFNSCR => 64 - case HTIFOffsetBits => site(CacheBlockOffsetBits) - case HTIFNCores => site(NTiles) - //Memory Parameters - case PAddrBits => 32 - case VAddrBits => 43 - case PgIdxBits => 13 - case ASIdBits => 7 - case PermBits => 6 - case PPNBits => site(PAddrBits) - site(PgIdxBits) - case VPNBits => site(VAddrBits) - site(PgIdxBits) - case MIFTagBits => 5 - case MIFDataBits => 128 - case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits) - case MIFDataBeats => 4 //Uncore Paramters case LNMasters => site(NBanks) case LNClients => site(NTiles)+1 @@ -96,13 +96,13 @@ class DefaultConfig extends ChiselConfig { case TLWriteMaskBits => 6 case TLWordAddrBits => 3 case TLAtomicOpBits => 4 - case NTiles => here[Int]("NTILES") - case NBanks => here[Int]("NBANKS") + case NTiles => Knob("NTILES") + case NBanks => Knob("NBANKS") case BankIdLSB => 5 case CacheBlockBytes => 64 case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes)) - case BuildDRAMSideLLC => () => { - val refill = site(TLDataBits)/site(MIFDataBits) + case UseBackupMemoryPort => true + case BuildDRAMSideLLC => (refill: Int) => { if(site[Boolean]("USE_DRAMSIDE_LLC")) { val tag = Mem(Bits(width = 152), 512, seqRead = true) val data = Mem(Bits(width = 64), 4096, seqRead = true) @@ -110,11 +110,11 @@ class DefaultConfig extends ChiselConfig { refill_cycles=refill, tagLeaf=tag, dataLeaf=data)) } else { Module(new DRAMSideLLCNull(16, refill)) } } - case BuildCoherentMaster => (id: Int) => { - if(!site[Boolean]("USE_DRAMSIDE_LLC")) { - Module(new L2CoherenceAgent(id), { case CacheName => "L2" }) - } else { + case BuildCoherenceMaster => (id: Int) => { + if(site[Boolean]("USE_L2_CACHE")) { Module(new L2HellaCache(id), { case CacheName => "L2" }) + } else { + Module(new L2CoherenceAgent(id), { case CacheName => "L2" }) } } case Coherence => { @@ -129,17 +129,20 @@ class DefaultConfig extends ChiselConfig { else new MICoherence(dir) } } - //DesignSpaceConstants //TODO KNOBS - case "NTILES" => 1 - case "NBANKS" => 1 - case "HTIF_WIDTH" => 16 case "ENABLE_SHARING" => true case "ENABLE_CLEAN_EXCLUSIVE" => true case "USE_DRAMSIDE_LLC" => true - case "NL2_REL_XACTS" => 1 - case "NL2_ACQ_XACTS" => 7 - case "NMSHRS" => 2 + case "USE_L2_CACHE" => false } } + override val knobVal:Any=>Any = { + case "NTILES" => 1 + case "NBANKS" => 1 + case "L2_REL_XACTS" => 1 + case "L2_ACQ_XACTS" => 7 + case "L1D_MSHRS" => 2 + case "L1D_SETS" => 128 + case "L1D_WAYS" => 4 + } } diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 505ee52d..3a393126 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -10,12 +10,19 @@ case object NBanks extends Field[Int] case object BankIdLSB extends Field[Int] case object CacheBlockBytes extends Field[Int] case object CacheBlockOffsetBits extends Field[Int] -case object BuildDRAMSideLLC extends Field[() => DRAMSideLLCLike] -case object BuildCoherentMaster extends Field[(Int) => CoherenceAgent] +case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike] +case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent] +case object UseBackupMemoryPort extends Field[Boolean] case object Coherence extends Field[CoherencePolicyWithUncached] -class OuterMemorySystem extends Module -{ +abstract trait TopLevelParameters extends UsesParameters { + val htifW = params(HTIFWidth) + val nTiles = params(NTiles) + val nBanks = params(NBanks) + val lsb = params(BankIdLSB) + val refillCycles = params(MIFDataBeats) +} +class OuterMemorySystem extends Module with TopLevelParameters { val io = new Bundle { val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip val htif = (new TileLinkIO).flip @@ -25,15 +32,14 @@ class OuterMemorySystem extends Module val mem_backup_en = Bool(INPUT) } - val refill_cycles = params(TLDataBits)/params(MIFDataBits) - val llc = params(BuildDRAMSideLLC)() - val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherentMaster)) - + // Create a simple NoC and points of coherence serialization val net = Module(new ReferenceChipCrossbarNetwork) + val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster)) net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end } masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } } + // Create a converter between TileLinkIO and MemIO val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) if(params(NBanks) > 1) { val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks))) @@ -42,107 +48,75 @@ class OuterMemorySystem extends Module } else { conv.io.uncached <> masterEndpoints.head.io.outer } - llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd) - llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refill_cycles) + + // Create a DRAM-side LLC + val llc = params(BuildDRAMSideLLC)(refillCycles) + llc.io.cpu.req_cmd <> Queue(conv.io.mem.req_cmd, 2) + llc.io.cpu.req_data <> Queue(conv.io.mem.req_data, refillCycles) conv.io.mem.resp <> llc.io.cpu.resp - - // mux between main and backup memory ports - val mem_serdes = Module(new MemSerdes(params(HTIFWidth))) - val mem_cmdq = Module(new Queue(new MemReqCmd, 2)) - mem_cmdq.io.enq <> llc.io.mem.req_cmd - mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready) - io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en - io.mem.req_cmd.bits := mem_cmdq.io.deq.bits - mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en - mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits - - val mem_dataq = Module(new Queue(new MemData, refill_cycles)) - mem_dataq.io.enq <> llc.io.mem.req_data - mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready) - io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en - io.mem.req_data.bits := mem_dataq.io.deq.bits - mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en - mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits - - llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid) - io.mem.resp.ready := Bool(true) - llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits) - - io.mem_backup <> mem_serdes.io.narrow + + // Create a SerDes for backup memory port + if(params(UseBackupMemoryPort)) { + VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup, + io.mem_backup_en, params(HTIFWidth)) + } else { + io.mem <> llc.io.mem + } } - -class Uncore extends Module -{ - require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits)) - val htif_width = params(HTIFWidth) +class Uncore extends Module with TopLevelParameters { val io = new Bundle { - val host = new HostIO(htif_width) + val host = new HostIO val mem = new MemIO - val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip - val htif = Vec.fill(params(NTiles)){new HTIFIO}.flip - val incoherent = Vec.fill(params(NTiles)){Bool()}.asInput - val mem_backup = new MemSerializedIO(htif_width) + val tiles = Vec.fill(nTiles){new TileLinkIO}.flip + val htif = Vec.fill(nTiles){new HTIFIO}.flip + val incoherent = Vec.fill(nTiles){Bool()}.asInput + val mem_backup = new MemSerializedIO(htifW) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(CSRs.reset)) - val outmemsys = Module(new OuterMemorySystem) - val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) - outmemsys.io.incoherent := incoherentWithHtif - htif.io.cpu <> io.htif - outmemsys.io.mem <> io.mem - outmemsys.io.mem_backup_en <> io.mem_backup_en - // Add networking headers and endpoint queues - def convertAddrToBank(addr: Bits): UInt = { - addr(params(BankIdLSB) + log2Up(params(NBanks)) - 1, params(BankIdLSB)) + // Used to hash physical addresses to banks + require(params(BankIdLSB) + log2Up(params(NBanks)) < params(MIFAddrBits)) + def addrToBank(addr: Bits): UInt = { + if(nBanks > 1) addr( lsb + log2Up(nBanks) - 1, lsb) + else UInt(0) } - (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { - case ((outer, client), i) => - outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, params(NBanks), convertAddrToBank _)) - outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, params(NBanks), convertAddrToBank _)) + val htif = Module(new HTIF(CSRs.reset)) // One HTIF module per chip + val outmemsys = Module(new OuterMemorySystem) // NoC, LLC and SerDes + + // Wire outer mem system to tiles and htif, adding + // networking headers and endpoint queues + (outmemsys.io.tiles :+ outmemsys.io.htif) // Collect outward-facing TileLink ports + .zip(io.tiles :+ htif.io.mem) // Zip them with matching ports from clients + .zipWithIndex // Index them + .map { case ((outer, client), i) => // Then use the index and bank hash to + // overwrite the networking header + outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, nBanks, addrToBank _)) + outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, nBanks, addrToBank _)) outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true)) client.grant <> Queue(outer.grant, 1, pipe = true) client.probe <> Queue(outer.probe) - } - - // pad out the HTIF using a divided clock - val hio = Module((new SlowIO(512)) { Bits(width = params(HTIFWidth)+1) }) - hio.io.set_divisor.valid := htif.io.scr.wen && htif.io.scr.waddr === 63 - hio.io.set_divisor.bits := htif.io.scr.wdata - htif.io.scr.rdata(63) := hio.io.divisor - - hio.io.out_fast.valid := htif.io.host.out.valid || outmemsys.io.mem_backup.req.valid - hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits)) - htif.io.host.out.ready := hio.io.out_fast.ready - outmemsys.io.mem_backup.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid - io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width) - io.host.out.bits := hio.io.out_slow.bits - io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width) - hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready) - - val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid - hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid - hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits) - io.host.in.ready := hio.io.in_slow.ready - outmemsys.io.mem_backup.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width) - outmemsys.io.mem_backup.resp.bits := hio.io.in_fast.bits - htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width) - htif.io.host.in.bits := hio.io.in_fast.bits - hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready) - io.host.clk := hio.io.clk_slow - io.host.clk_edge := Reg(next=io.host.clk && !Reg(next=io.host.clk)) + } + outmemsys.io.incoherent := (io.incoherent :+ Bool(true).asInput) + // Wire the htif to the memory port(s) and host interface io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr + htif.io.cpu <> io.htif + outmemsys.io.mem <> io.mem + if(params(UseBackupMemoryPort)) { + outmemsys.io.mem_backup_en := io.mem_backup_en + VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, + io.mem_backup, io.host, io.mem_backup_en, htifW) + } else { + htif.io.host.out <> io.host.out + htif.io.host.in <> io.host.in + } } -class TopIO extends Bundle { - val host = new HostIO(params(HTIFWidth)) +class TopIO extends Bundle { + val host = new HostIO val mem = new MemIO -} - -class VLSITopIO extends TopIO { val mem_backup_en = Bool(INPUT) val in_mem_ready = Bool(OUTPUT) val in_mem_valid = Bool(INPUT) @@ -150,20 +124,8 @@ class VLSITopIO extends TopIO { val out_mem_valid = Bool(OUTPUT) } -class MemDessert extends Module { - val io = new MemDesserIO(params(HTIFWidth)) - val x = Module(new MemDesser(params(HTIFWidth))) - io.narrow <> x.io.narrow - io.wide <> x.io.wide -} - -class Top extends Module { - - //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) - //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) - - val nTiles = params(NTiles) - val io = new VLSITopIO +class Top extends Module with TopLevelParameters { + val io = new TopIO val resetSigs = Vec.fill(nTiles){Bool()} val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) @@ -181,20 +143,20 @@ class Top extends Module { il := hl.reset tile.io.host.id := UInt(i) tile.io.host.reset := Reg(next=Reg(next=hl.reset)) - tile.io.host.pcr_req <> Queue(hl.pcr_req, 1) - hl.pcr_rep <> Queue(tile.io.host.pcr_rep, 1) - hl.ipi_req <> Queue(tile.io.host.ipi_req, 1) - tile.io.host.ipi_rep <> Queue(hl.ipi_rep, 1) + tile.io.host.pcr_req <> Queue(hl.pcr_req) + hl.pcr_rep <> Queue(tile.io.host.pcr_rep) + hl.ipi_req <> Queue(tile.io.host.ipi_req) + tile.io.host.ipi_rep <> Queue(hl.ipi_rep) hl.debug_stats_pcr := tile.io.host.debug_stats_pcr } io.host <> uncore.io.host - - uncore.io.mem_backup.resp.valid := io.in_mem_valid - - io.out_mem_valid := uncore.io.mem_backup.req.valid - uncore.io.mem_backup.req.ready := io.out_mem_ready - - io.mem_backup_en <> uncore.io.mem_backup_en io.mem <> uncore.io.mem + + if(params(UseBackupMemoryPort)) { + uncore.io.mem_backup.resp.valid := io.in_mem_valid + io.out_mem_valid := uncore.io.mem_backup.req.valid + uncore.io.mem_backup.req.ready := io.out_mem_ready + io.mem_backup_en <> uncore.io.mem_backup_en + } } diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 50184a0b..95290b46 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -1,82 +1,10 @@ package referencechip import Chisel._ -import uncore._ -import rocket._ -import DRAMModel._ -import DRAMModel.MemModelConstants._ -class FPGAOuterMemorySystem extends Module { - val io = new Bundle { - val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip - val htif = (new TileLinkIO).flip - val incoherent = Vec.fill(params(LNClients)){Bool()}.asInput - val mem = new MemIO - } - - val master = Module(new L2CoherenceAgent(0), {case CacheName => "L2"}) - val net = Module(new ReferenceChipCrossbarNetwork) - net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end } - net.io.masters.head <> master.io.inner - master.io.incoherent zip io.incoherent map { case (m, c) => m := c } - - val conv = Module(new MemIOUncachedTileLinkIOConverter(2)) - conv.io.uncached <> master.io.outer - io.mem.req_cmd <> Queue(conv.io.mem.req_cmd, 2) - io.mem.req_data <> Queue(conv.io.mem.req_data, params(TLDataBits)/params(MIFDataBits)) - conv.io.mem.resp <> Queue(io.mem.resp) -} - -class FPGAUncore extends Module { - val (htifw, nTiles) = (params(HTIFWidth),params(NTiles)) - val io = new Bundle { - val host = new HostIO(htifw) - val mem = new MemIO - val tiles = Vec.fill(nTiles){new TileLinkIO}.flip - val htif = Vec.fill(nTiles){new HTIFIO}.flip - val incoherent = Vec.fill(nTiles){Bool()}.asInput - } - val htif = Module(new HTIF(CSRs.reset)) - val outmemsys = Module(new FPGAOuterMemorySystem) - val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) - outmemsys.io.incoherent := incoherentWithHtif - htif.io.cpu <> io.htif - outmemsys.io.mem <> io.mem - - // Add networking headers and endpoint queues - (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { - case ((outer, client), i) => - outer.acquire <> Queue(TileLinkHeaderOverwriter(client.acquire, i, false)) - outer.release <> Queue(TileLinkHeaderOverwriter(client.release, i, false)) - outer.finish <> Queue(TileLinkHeaderOverwriter(client.finish, i, true)) - client.grant <> Queue(outer.grant, 1, pipe = true) - client.probe <> Queue(outer.probe) - } - - htif.io.host.out <> io.host.out - htif.io.host.in <> io.host.in -} - -class FPGATopIO extends TopIO - -class FPGATop extends Module { /* val ntiles = 1 val nmshrs = 2 - val htif_width = 16 - val co = new MESICoherence(new FullRepresentation(ntiles+1)) - implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, 1, ntiles+1) - implicit val as = AddressSpaceConfiguration(params[Int]("PADDR_BITS"), params[Int]("VADDR_BITS"), params[Int]("PGIDX_BITS"), params[Int]("ASID_BITS"), params[Int]("PERM_BITS")) - implicit val tl = TileLinkConfiguration(co = co, ln = ln, - addrBits = as.paddrBits-params[Int]("OFFSET_BITS"), - clientXactIdBits = log2Up(1+8), - masterXactIdBits = 2*log2Up(2*1+1), - dataBits = params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8, - writeMaskBits = params[Int]("WRITE_MASK_BITS"), - wordAddrBits = params[Int]("SUBWORD_ADDR_BITS"), - atomicOpBits = params[Int]("ATOMIC_OP_BITS")) - implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8) - implicit val mif = MemoryIFConfiguration(params[Int]("MEM_ADDR_BITS"), params[Int]("MEM_DATA_BITS"), params[Int]("MEM_TAG_BITS"), params[Int]("MEM_DATA_BEATS")) implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS")) val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2)) @@ -85,35 +13,6 @@ class FPGATop extends Module { fastMulDiv = false) */ - val nTiles = params(NTiles) - val io = new FPGATopIO - - val resetSigs = Vec.fill(nTiles){Bool()} - val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) - val uncore = Module(new FPGAUncore) - - for (i <- 0 until nTiles) { - val hl = uncore.io.htif(i) - val tl = uncore.io.tiles(i) - val il = uncore.io.incoherent(i) - - resetSigs(i) := hl.reset - val tile = tileList(i) - - tile.io.tilelink <> tl - il := hl.reset - tile.io.host.id := UInt(i) - tile.io.host.reset := Reg(next=Reg(next=hl.reset)) - tile.io.host.pcr_req <> Queue(hl.pcr_req) - hl.pcr_rep <> Queue(tile.io.host.pcr_rep) - hl.ipi_req <> Queue(tile.io.host.ipi_req) - tile.io.host.ipi_rep <> Queue(hl.ipi_rep) - } - - uncore.io.host <> io.host - uncore.io.mem <> io.mem -} - abstract class AXISlave extends Module { val aw = 5 val dw = 32 @@ -126,7 +25,7 @@ abstract class AXISlave extends Module { class Slave extends AXISlave { - val top = Module(new FPGATop) + val top = Module(new Top) val memw = top.io.mem.resp.bits.data.getWidth val htifw = top.io.host.in.bits.getWidth diff --git a/src/main/scala/vlsi.scala b/src/main/scala/vlsi.scala new file mode 100644 index 00000000..b5facb31 --- /dev/null +++ b/src/main/scala/vlsi.scala @@ -0,0 +1,66 @@ +package referencechip + +import Chisel._ +import uncore._ + +class MemDessert extends Module { + val io = new MemDesserIO(params(HTIFWidth)) + val x = Module(new MemDesser(params(HTIFWidth))) + io.narrow <> x.io.narrow + io.wide <> x.io.wide +} + +object VLSIUtils { + def doOuterMemorySystemSerdes(llc: MemPipeIO, mem: MemIO, + backup: MemSerializedIO, en: Bool, w: Int) { + val mem_serdes = Module(new MemSerdes(w)) + val wide = mem_serdes.io.wide + llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready) + mem.req_cmd.valid := llc.req_cmd.valid && !en + mem.req_cmd.bits := llc.req_cmd.bits + wide.req_cmd.valid := llc.req_cmd.valid && en + wide.req_cmd.bits := llc.req_cmd.bits + + llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready) + mem.req_data.valid := llc.req_data.valid && !en + mem.req_data.bits := llc.req_data.bits + wide.req_data.valid := llc.req_data.valid && en + wide.req_data.bits := llc.req_data.bits + + llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid) + llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits) + mem.resp.ready := Bool(true) + + backup <> mem_serdes.io.narrow + } + + def padOutHTIFWithDividedClock(htif: HTIFModuleIO, child: MemSerializedIO, + parent: MemSerializedIO, host: HostIO, + en: Bool, htifW: Int) { + val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) }) + hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63)) + hio.io.set_divisor.bits := htif.scr.wdata + htif.scr.rdata(63) := hio.io.divisor + + hio.io.out_fast.valid := htif.host.out.valid || child.req.valid + hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits)) + htif.host.out.ready := hio.io.out_fast.ready + child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid + host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW) + host.out.bits := hio.io.out_slow.bits + parent.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW) + hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htifW), host.out.ready, parent.req.ready) + + val mem_backup_resp_valid = en && parent.resp.valid + hio.io.in_slow.valid := mem_backup_resp_valid || host.in.valid + hio.io.in_slow.bits := Cat(mem_backup_resp_valid, host.in.bits) + host.in.ready := hio.io.in_slow.ready + child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW) + child.resp.bits := hio.io.in_fast.bits + htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW) + htif.host.in.bits := hio.io.in_fast.bits + hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready) + host.clk := hio.io.clk_slow + host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk)) + } +} diff --git a/uncore b/uncore index 44f51125..d12f3816 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 44f5112536350d37e7fe804ad9fe42c3516cb4c5 +Subproject commit d12f381645803a5c21bc0559494244ef6f2aad08 From 78ab83d224130be39684dda8237cda403837b410 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 28 Aug 2014 13:07:54 -0700 Subject: [PATCH 14/16] refactor fpga top/config --- src/main/scala/PublicConfigs.scala | 35 +++++++++++++++++++++++++++--- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- 3 files changed, 34 insertions(+), 5 deletions(-) diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala index 8fd57a18..e074b020 100644 --- a/src/main/scala/PublicConfigs.scala +++ b/src/main/scala/PublicConfigs.scala @@ -5,9 +5,6 @@ import uncore._ import rocket._ import rocket.Util._ -class DefaultVLSIConfig extends DefaultConfig -class DefaultFPGAConfig extends DefaultConfig -class DefaultCPPConfig extends DefaultConfig class DefaultConfig extends ChiselConfig { val top:World.TopDefs = { (pname,site,here) => pname match { @@ -145,4 +142,36 @@ class DefaultConfig extends ChiselConfig { case "L1D_WAYS" => 4 } } +class DefaultVLSIConfig extends DefaultConfig +class DefaultCPPConfig extends DefaultConfig +class FPGAConfig(default: ChiselConfig) extends ChiselConfig { + val top:World.TopDefs = { + (pname,site,here) => pname match { + case NSets => site(CacheName) match { + case "L1I" => 64 + case "L1D" => Knob("L1D_SETS") + } + case NWays => site(CacheName) match { + case "L1I" => 1 + case "L1D" => Knob("L1D_WAYS") + } + case FastMulDiv => false + case NITLBEntries => 4 + case NBTBEntries => 8 + case NDTLBEntries => 4 + case _ => default.top(pname,site,here) + } + } + override val knobVal:Any=>Any = { + case "NTILES" => 1 + case "NBANKS" => 1 + case "L2_REL_XACTS" => 1 + case "L2_ACQ_XACTS" => 7 + case "L1D_MSHRS" => 2 + case "L1D_SETS" => 64 + case "L1D_WAYS" => 1 + } +} + +class DefaultFPGAConfig extends FPGAConfig(new DefaultConfig) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 3a393126..acb7d0a9 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -58,7 +58,7 @@ class OuterMemorySystem extends Module with TopLevelParameters { // Create a SerDes for backup memory port if(params(UseBackupMemoryPort)) { VLSIUtils.doOuterMemorySystemSerdes(llc.io.mem, io.mem, io.mem_backup, - io.mem_backup_en, params(HTIFWidth)) + io.mem_backup_en, htifW) } else { io.mem <> llc.io.mem } diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 95290b46..5900fea8 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -64,7 +64,7 @@ class Slave extends AXISlave // write cr1 -> mem.resp (nonblocking) val in_count = Reg(init=UInt(0, log2Up(memw/dw))) - val rf_count = Reg(init=UInt(0, log2Up(params[Int]("CACHE_DATA_SIZE_IN_BYTES")*8/memw))) + val rf_count = Reg(init=UInt(0, log2Up(params(CacheBlockBytes)*8/memw))) require(memw % dw == 0 && isPow2(memw/dw)) val in_reg = Reg(top.io.mem.resp.bits.data) top.io.mem.resp.bits.data := Cat(io.in.bits, in_reg(in_reg.getWidth-1,dw)) From 8622eb0f5b9c9eaf92ccdf9deac2559a23bafcf3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 1 Sep 2014 13:34:15 -0700 Subject: [PATCH 15/16] bump rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 54fe89fe..29ef51b1 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 54fe89fe3bdc9e9cd2caf7adab68bb6bb81b2b9c +Subproject commit 29ef51b1b343667c6376468356c17c597033ce2d From 3250db0dd5ee95fa3ff64871c967240aa557f831 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 2 Sep 2014 12:37:44 -0700 Subject: [PATCH 16/16] bump uncore --- uncore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/uncore b/uncore index d12f3816..63451c17 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit d12f381645803a5c21bc0559494244ef6f2aad08 +Subproject commit 63451c170b21444a07e685fa3bb170acae8d538f