riscv/rocket-chip
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make sure TraceGen gets correct addresses

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This commit is contained in:
Howard Mao 2016-08-04 11:08:25 -07:00
parent 0a85e92652
commit 410e3e5366
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/TestConfigs.scala
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@ -210,8 +210,9 @@ class WithTraceGen extends Config(
val nWays = 1 val nWays = 1
val blockOffset = site(CacheBlockOffsetBits) val blockOffset = site(CacheBlockOffsetBits)
val baseAddr = site(GlobalAddrMap)("mem").start val baseAddr = site(GlobalAddrMap)("mem").start
val nBeats = site(MIFDataBeats)
List.tabulate(4 * nWays) { i => List.tabulate(4 * nWays) { i =>
Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset } Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
}.flatten.map(addr => baseAddr + BigInt(addr)) }.flatten.map(addr => baseAddr + BigInt(addr))
} }
case UseAtomics => true case UseAtomics => true