From 410e3e53667c092c4ffe0f141ca715800d60e2cc Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 4 Aug 2016 11:08:25 -0700
Subject: [PATCH] make sure TraceGen gets correct addresses

---
 src/main/scala/TestConfigs.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index 8837230e..cecde465 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -210,8 +210,9 @@ class WithTraceGen extends Config(
       val nWays = 1
       val blockOffset = site(CacheBlockOffsetBits)
       val baseAddr = site(GlobalAddrMap)("mem").start
+      val nBeats = site(MIFDataBeats)
       List.tabulate(4 * nWays) { i =>
-        Seq.tabulate(2) { j => (i * nSets + j * 8) << blockOffset }
+        Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
       }.flatten.map(addr => baseAddr + BigInt(addr))
     }
     case UseAtomics => true