tilelink2 RegisterRouterTest: don't couple fire into helpers
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@ -26,15 +26,13 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
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val wdata = UInt(INPUT, width = bits)
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val wdata = UInt(INPUT, width = bits)
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}
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}
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val rfire = io.rvalid && io.rready
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val wfire = io.wvalid && io.wready
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val reg = Reg(UInt(width = bits))
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val reg = Reg(UInt(width = bits))
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io.rvalid := rvalid(rfire)
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io.rvalid := rvalid(io.rready)
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io.wready := wready(wfire)
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io.wready := wready(io.wvalid)
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io.rdata := reg
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io.rdata := reg
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when (wfire) { reg := io.wdata }
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when (io.wvalid && io.wready) { reg := io.wdata }
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}
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}
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object RRTestCombinational
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object RRTestCombinational
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@ -43,19 +41,19 @@ object RRTestCombinational
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def always: Bool => Bool = _ => Bool(true)
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def always: Bool => Bool = _ => Bool(true)
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def random: Bool => Bool = { fire =>
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def random: Bool => Bool = { ready =>
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seed = seed + 1
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seed = seed + 1
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val lfsr = LFSR16Seed(seed)
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val lfsr = LFSR16Seed(seed)
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val reg = RegInit(Bool(true))
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val valid = RegInit(Bool(true))
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reg := Mux(reg, !fire, lfsr(0) && lfsr(1))
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valid := Mux(valid, !ready, lfsr(0) && lfsr(1))
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reg
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valid
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}
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}
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def delay(x: Int): Bool => Bool = { fire =>
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def delay(x: Int): Bool => Bool = { ready =>
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val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
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val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
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val ready = reg === UInt(0)
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val valid = reg === UInt(0)
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reg := Mux(fire, UInt(x), Mux(ready, UInt(0), reg - UInt(1)))
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reg := Mux(ready && valid, UInt(x), Mux(valid, UInt(0), reg - UInt(1)))
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ready
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valid
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}
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}
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def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
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def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {
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