diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
index 8c226f01..04d73cf2 100644
--- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
@@ -26,15 +26,13 @@ class RRTestCombinational(val bits: Int, rvalid: Bool => Bool, wready: Bool => B
     val wdata  = UInt(INPUT, width = bits)
   }
 
-  val rfire = io.rvalid && io.rready
-  val wfire = io.wvalid && io.wready
   val reg = Reg(UInt(width = bits))
 
-  io.rvalid := rvalid(rfire)
-  io.wready := wready(wfire)
+  io.rvalid := rvalid(io.rready)
+  io.wready := wready(io.wvalid)
 
   io.rdata := reg
-  when (wfire) { reg := io.wdata }
+  when (io.wvalid && io.wready) { reg := io.wdata }
 }
 
 object RRTestCombinational
@@ -43,19 +41,19 @@ object RRTestCombinational
 
   def always: Bool => Bool = _ => Bool(true)
 
-  def random: Bool => Bool = { fire =>
+  def random: Bool => Bool = { ready =>
     seed = seed + 1
     val lfsr = LFSR16Seed(seed)
-    val reg = RegInit(Bool(true))
-    reg := Mux(reg, !fire, lfsr(0) && lfsr(1))
-    reg
+    val valid = RegInit(Bool(true))
+    valid := Mux(valid, !ready, lfsr(0) && lfsr(1))
+    valid
   }
 
-  def delay(x: Int): Bool => Bool = { fire =>
+  def delay(x: Int): Bool => Bool = { ready =>
     val reg = RegInit(UInt(0, width = log2Ceil(x+1)))
-    val ready = reg === UInt(0)
-    reg := Mux(fire, UInt(x), Mux(ready, UInt(0), reg - UInt(1)))
-    ready
+    val valid = reg === UInt(0)
+    reg := Mux(ready && valid, UInt(x), Mux(valid, UInt(0), reg - UInt(1)))
+    valid
   }
 
   def combo(bits: Int, rvalid: Bool => Bool, wready: Bool => Bool): RegField = {