From 3ee514492309866f485585904a6ab30251299ccf Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 27 May 2016 12:24:17 -0700
Subject: [PATCH] Fix TLB tag check logic when ASIDs are present

---
 rocket/src/main/scala/tlb.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 909f49e1..99742a56 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -92,7 +92,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
   val r_refill_waddr = Reg(tag_cam.io.write_addr)
   val r_req = Reg(new TLBReq)
   
-  val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn).toUInt
+  val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
   tag_cam.io.tag := lookup_tag
   tag_cam.io.write := state === s_wait && io.ptw.resp.valid
   tag_cam.io.write_tag := r_refill_tag