From 3df401eef70eeeba502f11cde9f86dc9a3681e78 Mon Sep 17 00:00:00 2001
From: Jack Koenig <koenig@sifive.com>
Date: Tue, 12 Dec 2017 18:46:51 -0800
Subject: [PATCH] Bump chisel3 and firrtl and bump sbt to version 1.0.4

sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
---
 build.sbt                   | 9 ++++++---
 chisel3                     | 2 +-
 emulator/Makefrag-verilator | 2 +-
 firrtl                      | 2 +-
 project/build.properties    | 2 +-
 project/plugins.sbt         | 2 +-
 vsim/Makefrag-verilog       | 2 +-
 7 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/build.sbt b/build.sbt
index 2feead24..2fbb499d 100644
--- a/build.sbt
+++ b/build.sbt
@@ -2,7 +2,10 @@
 
 import sbt.complete._
 import sbt.complete.DefaultParsers._
-import xerial.sbt.Pack._
+import xerial.sbt.pack._
+import sys.process._
+
+enablePlugins(PackPlugin)
 
 lazy val commonSettings = Seq(
   organization := "berkeley",
@@ -26,7 +29,7 @@ lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
 lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
 val setMake = NotSpace ~ ( Space ~> NotSpace )
 
-val chipSettings = packAutoSettings ++ Seq(
+val chipSettings = Seq(
   addons := {
     val a = sys.env.getOrElse("ROCKETCHIP_ADDONS", "")
     println(s"Using addons: $a")
@@ -38,6 +41,6 @@ val chipSettings = packAutoSettings ++ Seq(
     val jobs = java.lang.Runtime.getRuntime.availableProcessors
     val (makeDir, target) = setMake.parsed
     (run in Compile).evaluated
-    s"make -C $makeDir  -j $jobs $target" !
+    s"make -C $makeDir  -j $jobs $target".!
   }
 )
diff --git a/chisel3 b/chisel3
index 30e8eb55..9f504b99 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 30e8eb552a29b22bc23faa06f5661da6129188b2
+Subproject commit 9f504b9926d38d11fb8003c72360ff11d24b5ef6
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 021e131c..a83426ba 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -10,7 +10,7 @@ verilog = \
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 %.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
diff --git a/firrtl b/firrtl
index 40dda493..8ab501e7 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 40dda493a277f721306d428ee967dcb670813275
+Subproject commit 8ab501e7527139a4ee8d0b38f9b4384551387043
diff --git a/project/build.properties b/project/build.properties
index c091b86c..394cb75c 100644
--- a/project/build.properties
+++ b/project/build.properties
@@ -1 +1 @@
-sbt.version=0.13.16
+sbt.version=1.0.4
diff --git a/project/plugins.sbt b/project/plugins.sbt
index a7f364fd..ed9ac0ee 100644
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -6,7 +6,7 @@ addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
 
 addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
 
-addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.8.0")
+addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
 
 addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
 
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index d0571eeb..7514be2e 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
 
 $(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)