debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN
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@ -239,7 +239,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
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--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
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--s $(RISCV)/share/openocd/scripts" \
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--32 \
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$(abspath $(TOP))/scripts/RocketSim.py \
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$(abspath $(TOP))/scripts/RocketSim32.py \
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$(JTAG_DTM_TEST)
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date > $@
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@ -249,7 +249,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
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--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
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--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
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--64 \
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$(abspath $(TOP))/scripts/RocketSim.py \
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$(abspath $(TOP))/scripts/RocketSim64.py \
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$(JTAG_DTM_TEST)
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date > $@
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@ -259,7 +259,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
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--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
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--s $(RISCV)/share/openocd/scripts" \
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--32 \
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$(abspath $(TOP))/scripts/RocketSim.py \
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$(abspath $(TOP))/scripts/RocketSim32.py \
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$(JTAG_DTM_TEST)
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date > $@
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@ -269,7 +269,7 @@ stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
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--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
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--s $(RISCV)/share/openocd/scripts" \
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--64 \
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$(abspath $(TOP))/scripts/RocketSim.py \
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$(abspath $(TOP))/scripts/RocketSim64.py \
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$(JTAG_DTM_TEST)
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date > $@
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