riscv/rocket-chip
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debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN

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Megan Wachs committed 2018-01-05 16:10:13 -08:00
1 parent bd5fe5d22e
commit 3de9a04272
3 files changed
+48 -4
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regression/Makefile
+4 -4
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@@ -239,7 +239,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--32 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim32.py \
$(JTAG_DTM_TEST)
date > $@
@@ -249,7 +249,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
--64 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim64.py \
$(JTAG_DTM_TEST)
date > $@
@@ -259,7 +259,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--32 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim32.py \
$(JTAG_DTM_TEST)
date > $@
@@ -269,7 +269,7 @@ stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/emulator$(JTAG_S
--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
--s $(RISCV)/share/openocd/scripts" \
--64 \
$(abspath $(TOP))/scripts/RocketSim.py \
$(abspath $(TOP))/scripts/RocketSim64.py \
$(JTAG_DTM_TEST)
date > $@