From 3de9a042727ed0e27968707094a32350ef0bf1df Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 15 Nov 2017 16:05:36 -0800
Subject: [PATCH] debug regression: until XLEN fix is merged into riscv-tests,
 have to explicitly state the XLEN

---
 regression/Makefile    |  8 ++++----
 scripts/RocketSim32.py | 22 ++++++++++++++++++++++
 scripts/RocketSim64.py | 22 ++++++++++++++++++++++
 3 files changed, 48 insertions(+), 4 deletions(-)
 create mode 100644 scripts/RocketSim32.py
 create mode 100644 scripts/RocketSim64.py

diff --git a/regression/Makefile b/regression/Makefile
index 09e4ce32..48f114df 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -239,7 +239,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	--s $(RISCV)/share/openocd/scripts" \
 	--32 \
-	$(abspath $(TOP))/scripts/RocketSim.py \
+	$(abspath $(TOP))/scripts/RocketSim32.py \
 	$(JTAG_DTM_TEST)
 	date > $@
 
@@ -249,7 +249,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
 	--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
 	--s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
 	--64 \
-	$(abspath $(TOP))/scripts/RocketSim.py \
+	$(abspath $(TOP))/scripts/RocketSim64.py \
 	$(JTAG_DTM_TEST)
 	date > $@
 
@@ -259,7 +259,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp:  stamps/%/emulator$(JTAG_S
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	--s $(RISCV)/share/openocd/scripts" \
 	--32 \
-	$(abspath $(TOP))/scripts/RocketSim.py \
+	$(abspath $(TOP))/scripts/RocketSim32.py \
 	$(JTAG_DTM_TEST)
 	date > $@
 
@@ -269,7 +269,7 @@ stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp:  stamps/%/emulator$(JTAG_S
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	--s $(RISCV)/share/openocd/scripts" \
 	--64 \
-	$(abspath $(TOP))/scripts/RocketSim.py \
+	$(abspath $(TOP))/scripts/RocketSim64.py \
 	$(JTAG_DTM_TEST)
 	date > $@
 
diff --git a/scripts/RocketSim32.py b/scripts/RocketSim32.py
new file mode 100644
index 00000000..55482121
--- /dev/null
+++ b/scripts/RocketSim32.py
@@ -0,0 +1,22 @@
+import targets
+import testlib
+
+class RocketSimHart(targets.Hart):
+    xlen = 32
+    # This isn't generically true, but it's true enough for the Default*Configs in this code for now.
+    # to get these tests to pass.
+    ram = 0x80000000
+    ram_size = 0x4000
+    instruction_hardware_breakpoint_count = 2
+    pass
+
+class RocketSim(targets.Target):
+    harts = [RocketSimHart()]
+    timeout_sec = 6000
+    server_timeout_sec = 60*60
+    openocd_config_path = "RocketSim.cfg"
+
+    def create(self):
+        print "STARTING A SIMULATION"
+        print self.sim_cmd
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/scripts/RocketSim64.py b/scripts/RocketSim64.py
new file mode 100644
index 00000000..0e89a51c
--- /dev/null
+++ b/scripts/RocketSim64.py
@@ -0,0 +1,22 @@
+import targets
+import testlib
+
+class RocketSimHart(targets.Hart):
+    # This isn't generically true, but it's true enough for the Default*Configs in this code for now.
+    # to get these tests to pass.
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 0x4000
+    instruction_hardware_breakpoint_count = 2
+    pass
+
+class RocketSim(targets.Target):
+    harts = [RocketSimHart()]
+    timeout_sec = 6000
+    server_timeout_sec = 60*60
+    openocd_config_path = "RocketSim.cfg"
+
+    def create(self):
+        print "STARTING A SIMULATION"
+        print self.sim_cmd
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)