riscv/rocket-chip
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Refactored coherence as member rather than trait. MI and MEI protocols.

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This commit is contained in:
Henry Cook
2012-04-10 00:09:58 -07:00
parent 9c8f849f50
commit 3cdd166153
8 changed files with 331 additions and 80 deletions
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8
rocket/src/main/scala/tile.scala
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@ -4,7 +4,7 @@ import Chisel._
import Node._
import Constants._
class Tile extends Component
class Tile(co: CoherencePolicyWithUncached) extends Component
{
val io = new Bundle {
val tilelink = new ioTileLink
@ -12,8 +12,8 @@ class Tile extends Component
}
val cpu = new rocketProc(resetSignal = io.host.reset)
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val dcache = new HellaCacheUniproc
val icache = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache(co)
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem
@ -30,7 +30,7 @@ class Tile extends Component
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}