riscv/rocket-chip
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Refactored coherence as member rather than trait. MI and MEI protocols.

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This commit is contained in:
Henry Cook
2012-04-10 00:09:58 -07:00
parent 9c8f849f50
commit 3cdd166153
8 changed files with 331 additions and 80 deletions
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4
rocket/src/main/scala/icache.scala
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@ -27,7 +27,7 @@ class ioRocketICache extends Bundle()
// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
// parameters :
// lines = # cache lines
class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCoherence
class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component
{
val io = new ioRocketICache();
@ -136,7 +136,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component with FourStateCohere
rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
io.cpu.resp_data := data_mux.io.out
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits.x_type := xactInitReadUncached
io.mem.xact_init.bits.x_type := co.getTransactionInitTypeOnUncachedRead
io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
io.mem.xact_finish <> finish_q.io.deq