riscv/rocket-chip
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By default, use same TileLink width everywhere

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When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
This commit is contained in:
Andrew Waterman
2016-05-25 18:01:57 -07:00
parent 976d4d3184
commit 3cc236e9c4
7 changed files with 10 additions and 5 deletions
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2
chisel3

Submodule chisel3 updated: d742d70a05...3b10267257

2
groundtest

Submodule groundtest updated: 49b713c4fb...f44383cd9b

2
junctions

Submodule junctions updated: f1c609d74a...9522bc5a2a

2
rocket

Submodule rocket updated: 05b951ba6f...a2c51cfabe

3
src/main/scala/Configs.scala
View File

@ -260,6 +260,7 @@ class BaseConfig extends Config (
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)), if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2, maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = site(MIFDataBeats),
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") => case TLKey("L2toMC") =>
TileLinkParameters( TileLinkParameters(
@ -271,6 +272,7 @@ class BaseConfig extends Config (
maxClientXacts = 1, maxClientXacts = 1,
maxClientsPerPort = site(NAcquireTransactors) + 2, maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1, maxManagerXacts = 1,
dataBeats = site(MIFDataBeats),
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy( case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2, maxClientXacts = site(NAcquireTransactors) + 2,
@ -287,6 +289,7 @@ class BaseConfig extends Config (
maxClientXacts = 4, maxClientXacts = 4,
maxClientsPerPort = 1, maxClientsPerPort = 1,
maxManagerXacts = 1, maxManagerXacts = 1,
dataBeats = site(MIFDataBeats),
dataBits = site(CacheBlockBytes) * 8) dataBits = site(CacheBlockBytes) * 8)
} }
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats)) case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))

2
src/main/scala/TestConfigs.scala
View File

@ -23,6 +23,7 @@ class WithGroundTest extends Config(
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)), if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = 2, maxClientsPerPort = 2,
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = site(MIFDataBeats),
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
case BuildTiles => { case BuildTiles => {
val groundtest = if (site(XLen) == 64) val groundtest = if (site(XLen) == 64)
@ -42,6 +43,7 @@ class WithGroundTest extends Config(
case TohostAddr => BigInt("80001000", 16) case TohostAddr => BigInt("80001000", 16)
case RoccNCSRs => site(GroundTestCSRs).size case RoccNCSRs => site(GroundTestCSRs).size
case UseFPU => false case UseFPU => false
case UseAtomics => true
case _ => throw new CDEMatchError case _ => throw new CDEMatchError
}) })

2
uncore

Submodule uncore updated: 1bb32abf97...e37eea2c33