riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

clint: undefined registers must be zero (#480)

Browse Source 
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
This commit is contained in:
Wesley W. Terpstra 2016-12-05 17:11:53 -08:00 committed by GitHub
parent f3d0692619
commit 3c9718ec8f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/devices/Prci.scala
View File

@ -84,7 +84,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
/** Power, Reset, Clock, Interrupt */
// Magic TL2 Incantation to create a TL2 Slave
class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters)
extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)(
new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
{