From 3c9718ec8f148f55b7ee31f8f130f44d90c471d4 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 5 Dec 2016 17:11:53 -0800 Subject: [PATCH] clint: undefined registers must be zero (#480) This is needed so that SMP-safe boot loaders can safely read/write to the IPI register of non-existent harts. --- src/main/scala/uncore/devices/Prci.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala index 5c38987c..d5c36900 100644 --- a/src/main/scala/uncore/devices/Prci.scala +++ b/src/main/scala/uncore/devices/Prci.scala @@ -84,7 +84,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep /** Power, Reset, Clock, Interrupt */ // Magic TL2 Incantation to create a TL2 Slave class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters) - extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)( + extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)( new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)( new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule) {