From 3bb258022307376bfdba6eeabb72bc12a7d394d6 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 21 Sep 2016 18:06:39 -0700 Subject: [PATCH] tilelink2 Monitor: detect minLatency violations --- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index fe1107a8..fa77e26b 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -438,6 +438,10 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source val a_bypass = bypass && bundle.d.valid && d_last val d_bypass = bypass && bundle.a.valid && a_last + if (edge.manager.minLatency > 0) { + assert(!bypass || !bundle.a.valid || !bundle.d.valid, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra) + } + when (bundle.a.fire()) { a_counter := Mux(a_first, a_beats1, a_counter - UInt(1)) when (a_last) { inflight(bundle.a.bits.source) := Bool(true) }