From 3b4680a8349444db47d9462f7119bce39260d6d7 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 17 Mar 2012 14:03:33 -0700 Subject: [PATCH] add vitlb exception port --- rocket/src/main/scala/cpu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 7acacb29..21a27d3e 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -159,7 +159,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) vu.io.imem_req.ready := Bool(true) vu.io.imem_resp.valid := io.vimem.resp_val vu.io.imem_resp.bits := io.vimem.resp_data - // handle vitlb.io.cpu.exception + vu.io.vitlb_exception := vitlb.io.cpu.exception io.vimem.itlb_miss := vitlb.io.cpu.resp_miss // hooking up vector command queues