riscv/rocket-chip
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add AXI to AHB converter and more conformant HASTI RAM

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This commit is contained in:
Howard Mao
2016-04-28 18:56:27 -07:00
parent a875eb9c31
commit 3b0e9167fa
4 changed files with 6 additions and 3 deletions
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2
groundtest

Submodule groundtest updated: 11b046a0bc...49b713c4fb

2
junctions

Submodule junctions updated: 7448c27267...7aaaa59d96

3
src/main/scala/Configs.scala
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@ -118,6 +118,9 @@ class DefaultConfig extends Config (
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)), addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits))) idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
} }
case HastiKey => HastiParameters(
dataBits = site(XLen),
addrBits = site(PAddrBits))
//Params used by all caches //Params used by all caches
case NSets => findBy(CacheName) case NSets => findBy(CacheName)
case NWays => findBy(CacheName) case NWays => findBy(CacheName)

2
uncore

Submodule uncore updated: 8e21cc781f...f236b5fa0d