From 3b0e9167faf89a1042711fd0381b3cfaee0e6ff0 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 28 Apr 2016 18:56:27 -0700 Subject: [PATCH] add AXI to AHB converter and more conformant HASTI RAM --- groundtest | 2 +- junctions | 2 +- src/main/scala/Configs.scala | 3 +++ uncore | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/groundtest b/groundtest index 11b046a0..49b713c4 160000 --- a/groundtest +++ b/groundtest @@ -1 +1 @@ -Subproject commit 11b046a0bc0c23fa23ced1fa890af183922d2ec4 +Subproject commit 49b713c4fbb6660b6d86a7e19ea048d6d7aeb17a diff --git a/junctions b/junctions index 7448c272..7aaaa59d 160000 --- a/junctions +++ b/junctions @@ -1 +1 @@ -Subproject commit 7448c2726721b0260ce56e1dfc03d6f7786a2f9b +Subproject commit 7aaaa59d96f998d38d0969894cf9ec0e1fcfed22 diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index 5c2fa6d5..ac1198b7 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -118,6 +118,9 @@ class DefaultConfig extends Config ( addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)), idBits = Dump("MEM_ID_BITS", site(MIFTagBits))) } + case HastiKey => HastiParameters( + dataBits = site(XLen), + addrBits = site(PAddrBits)) //Params used by all caches case NSets => findBy(CacheName) case NWays => findBy(CacheName) diff --git a/uncore b/uncore index 8e21cc78..f236b5fa 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 8e21cc781f5fd1fdfd94a579fb5a1392ed664e99 +Subproject commit f236b5fa0dbc3ab488b5ac021862808f11361524