add AXI to AHB converter and more conformant HASTI RAM

src/main/scala/Configs.scala

@@ -118,6 +118,9 @@ class DefaultConfig extends Config (
           addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
           idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
       }
+      case HastiKey => HastiParameters(
+                        dataBits = site(XLen),
+                        addrBits = site(PAddrBits))
       //Params used by all caches
       case NSets => findBy(CacheName)
       case NWays => findBy(CacheName)